Does the Intersil 6100 do interrupts differently from other PDP-8s?

Question

As I recall, the original PDP-8 actually does a jsr 0000 when an interrupt happens, so that the interrupt service routine started at address 0001. I think that saves a few gates, since the instruction decoder can also be used to handle an interrupt, a bit like the 6502.

But since space in the zero page is usually at a premium, and since the ISA encourages data to be put there, it makes no sense for this region of memory to also host an interrupt service routine. This I consider one of the mistakes in the design of the PDP-8.

Now, about a much later implementation, the Intersil 6100, the Wikipedia page says:

When the interrupt is tripped, the CPU stores the current PC in 0000, and then jumps to the location stored in 0001.

The wording is a little hazy, but seems to imply that 0001 contains a pointer to the interrupt service routine. So did the Intersil 6100 designers consider this design mistake, and correct that by letting location 0001 point to the ISR? Or am I reading this wrong, and the ISR actually starts at 0001 like the other PDP-8s?

Answer 1

The Intersil 6100 manual on bitsavers clearly says

Instruction fetch from 0001 of mem

in figure 11 (page 19). It doesn't say "data fetch, and instruction fetch from address just read".

So it is indeed a JMS, and the Wikipedia wording is misleading (well, it's Wikipedia).

I also would have been very surprised if they had changed this in the Intersil 6100 - after all, the goal should have been to let existing software run unmodified. Having to rewrite everything that deals with interrupts is quite painful.

Edit

Following a suggestion by @tofro, there is an ISR example in the manual on page 96 where address 0001 just contains an IOF (interrupt off) instead of the indirect jump that would normally be required. This only works together with the Parallel Interface Element (PIE) Intersil 6101 chip, and is described as follows on page 51:

The IM6100 activates the INTGNT signal high when an INTREO is acknowledged. The INTGNT is reset by executing any IOT instruction. The PIEs use the INTGNT signal to freeze the priority network and to uniquely specify the PIE with the highest priority interrupt request. The PIE with the highest priority request sends a unique vector address to the IM6100 when the processor executes the first IOT instruction after the INTGNT. It is recommended that the internal processor instruction, Interrupt Off (IOF - 6002_8) be used for vectoring. IOF, in this context, is a NOP, since the interrupt system is automatically disabled after an interrupt grant.

The 12-bit vector address generated by the PIE consists of 10 high order bits from the vector register, defined by the user during system initialization, and two low order bits which indicate the sense input that generated the interrupt. Therefore, if the instruction in location 0001_8 is IOF - 6002_8, the processor will branch to 1 of 4 locations, depending on which of the sense lines within a PIE generated the request. Each one of these locations must contain a Jump instruction pointing to the specific service routine for the corresponding sense input.

So Intersil did fix the zero page usage problem, and even allowed for chainable vectored interrupts, but with an additional chip (which would need custom software anyhow) instead of modifying the CPU, preserving software compatibility.

Answer 2

Wikipedia seems to be wrong here. From the Intersil Manual:

DEVICE INTERRUPT GRANT TIMING The current content of the Program Counter, PC, is deposited in location 0000 of the memory and the program fetches the instruction from location 0001...

That clearly implies to me there is no address stored at 0001.

Beyond that, there's not much of a difference between storing an address at 0001 or a JMP instruction