What are the circuits captured on this photo of the NES PPU die?

Question

I found a die photo of the NES video chip: http://visual6502.org/images/RP2C02/NES_RP2C02_G_8F1_1B_20x_1600w.jpg

I think the big block of fairly regular circuitry at the bottom left is the sprites? There is an 8x8-ness about it, and the NES has 8 sprites per scan line.

The big block of even more regular circuitry at the top right looks like RAM. What did the PPU store, that would take up that much space?

The irregular circuitry at the top left, I'm guessing implements tiles, the other major feature of the PPU.

Anyone have any idea what the semi-regular circuitry at the bottom right might be?

Though it's hard to be sure about scale, the whole chip kind of looks smaller (in terms of eyeball guess at transistor count) than the VIC-II. As I understand it, the VIC-II came out a year earlier, implemented in 5-micron CMOS, was a big complex chip for its time (best guess maybe 15k transistors), had initial yield problems. Maybe Nintendo went for a smaller chip because they didn't feel they could have an interim period of charging $595 for the machine the way Commodore did? Having only one mode would also help some.

But the thing I am most curious about is how small the sprite circuitry is compared to the VIC-II. Granted the sprites are smaller, but still 8 pixels 3 colors = 2 bytes, compared to 12 pixels 3 colors = 3 bytes, so I would've expected maybe 2/3 the size, but it's actually about 1/4 of the chip compared to 3/4, so that's more like 1/3 the relative size, and that of a chip that looks smaller. How?

Answer 1

There's been a simulation of the RP2C02 chip created called Visual 2C02. It based on the same code that is used to make Visual 6502. It's author provided several images of the chips layers including one describing the purpose of various regions on the chip.

Since the text in the regions image can be very hard to read given the high resolution of the image, I've created a version of the Visual6502.org's chip scan in your question with the regions labelled:

So big block of regular circuitry on the bottom left is the Evaluated Sprite Data. The big block of even more regular circuitry at the top right is the Sprite RAM with the Sprite RAM Column Address Decoder in between. The irregular circuitry at the top left implements various functions, not all of which have been identified, but include regions labelled Analog Video Signal Generator, I/O Controller (?), Palette RAM, Horizontal and Vertical position counter, and CPU I/O Decoder ($2000-$2007). The semi-regular circuitry at the bottom right has also not been fully identified but the labels given there are VRAM Address (V), VRAM Address (T) + fine X scroll and Background render pipeline.

Answer 2

The RP2C02 was manufactured in 6µm. As far as I know the regions are this:

The regular structures in the top left should be at least two counters (vertical) and CPU address decoder (to the right)

Top right are two symmetric RAM blocks and its address decoder in between. Each one seems to be 32x32 bits, or 128 byte. This adds up to 256 bytes, or exactly what the sprite data is. The structure to the left would be buffers for loading/reading them. Maybe it also includes the 32 byte of sprite attributes - I have a hard time counting them.

The rectangular block on the middle left side above the large area is again some RAM, maybe colour palette? That would be 32 bytes, which would make it rather similar in density with the sprite RAM. To the top and right is decode/access logic.

The lower right seems like something that combines data and serializes it. Maybe that's the rendering pipeline combining the tile data read from RAM with prepared sprite data, before outputting it. There are two large counters above which may handle (external) RAM access.

Now for the huge block(s) on the lower left. While it looks RAM like, it contains way too many transistors and connections to be a simple RAM. That's a lot of logic. Even considering that it might be dual port (not so likely) wouldn't account for that. The structure direct above looks quite like a (priority) decoder. So my assumption would be that this is the secondary OAM holding the preprocessed 8 sprites that can be displayed on a line. The logic becomes plausible with the rather complex process of sprite data preparation the PPU does (see here and here). There is a lot of comparison and priority decisions to be made in real time per pixel.

Caveat: all above are just guesses from what I think I see in that scan, combined with what I know about the PPU.