Based on the fact that when you build a computer that evaluates the upper 8 address lines on an I/O cycle (and can use 16-bit I/O addresses), you can then unfortunately no longer use the block input and block output commands (as B is used as a repeat count), I think we can safely assume it was not intended that port address evaluation would take A8-A15 into account when the chip was designed.
In case a designer would decide to actually evaluate the upper address lines on an I/O cycle, the fact that
OUT <PORT>,A puts the contents of the accumulator on A8-A15 is not very useful, as A would hold the byte to output.
OUT (C),A could be useful and actually is used sometimes, like on the ZX-81 and on the Amstrad CPC range that use 16-bit I/O addresses (thus generally inhibiting any use of the former, as well as the block I/O commands). The sad fact that the CPC doesn't really make good use of its "enhanced" 16-bit I/O port address range is a different story, though)
The Zilog Z80 manual of 2016 (!) clearly states
In all Register Indirect input output instructions, including block I/O transfers, the contents of the C Register are transferred to the lower half of the address bus (device address) while the contents of Register B are transferred to the upper half of the address bus.
The same manual also very clearly states in the description of the /IOREQ signal (emphasis mine):
IORQ. Input/Output Request (output, active Low, tristate). IORQ indicates that the lower half of the address bus holds a valid I/O address for an I/O read or write operation.
The same manual shows A0-15 in the description of the I/O cycle and labels this "I/O address", which is, at least, somewhat misleading.
An older (1979) MOSTEK Z80 manual I found, shows only A0-A7 in the I/O cycle diagrams as port address, but does state the fact that register B is put to the upper half of the address bus on an I/O cycle.
I would neither suspect a design bug nor a documentation problem: The behavior is very clearly documented, apparently even in early manuals. It is also implied you simply shouldn't evaluate the upper 8 address lines on an I/O cycle. You still can, but if you do so, you will not be able to make sensible use of some of the I/O instructions.