If I attach a 16 KIB EEPROM to a 6502 or similar, and put some kind of operating system on it, it will run fine, but won't have access to any other chips. So, when a Commodore VIC20 had 5k of ram and 8+8k of ROM, how did it make the rom/ram chips know that its their turn and how did it translate the 16 bit adress signal into a signal in their range? And if it accomplishes that, that explains how memory mapping worked, because it can easily switch chips.
I'm not really sure how this question is meant, so this is maybe less of an answer as an attempt to understand the question first and answer accordingly.
If I attach a 16 KiB EEPROM to a 6502 or similar, and put some kind of operating system on it, it will run fine, but won't have access to any other form of memory.
You may still need logic to assign the ROM to some memory location, as well as to access other memory or I/O (which is memory-mapped on a 6502 anyway). Also, a 6502 won't be of much use without at least a little bit of RAM. Similarly, some I/O to let it spread its message (*1) may be a good idea.
So, when a Commodore VIC20 had 5k of ram and 8+8k of ROM, how did it make the rom/ram chips know that it's their turn, and how did it translate the 16-bit address signal into a signal in their range?
Each of these needs only a part of the default address range on a 6502 (or other CPU with 16 bit address space). 5+8+8 KiB = 21 KiB, which fits nicely into 64 KiB even leaving much space unused. Each of these memory chunks (RAM, ROM, ROM) need only a maximum 13 bit wide address (2^13 = 8096). So the remaining 3 bits of an address (usually the highest value ones) can be used to generate a select signal to each of these areas.
Most common is the use of a 74138 1-of-8 decoder, which turns these 3 bits into 8 lines that could select either memory (or I/O) chip.
Keep in mind, on a 6502 ROM must go up (for Reset vector access) and RAM down (for ZP and Stack). So RAM would be the uppermost two. So the lowest output would be fine to select the RAM, while the ROM needs to be hooked to the uppermost. As for now, the use of 8 KiB may be well enough - and simplify the setup much - so the highest address bit will be unused and should be grounded (*3,4).
Next to add RAM, for example a 6264 which gives you convenient 8 KiB that could be directly hooked up to the lowest 74138 output without further logic.
The remaining 74138 output lines could be used as a very crude output logic by attaching six LEDs. Now every access between
DFFF would light one of these diodes for a little moment. Doing this in a loop will make them light continuously. Really is a simple 4 chip 6502 system able to tell you its existence with Blinkenlights :))
And if it accomplishes that, that explains how memory mapping worked, because it can easily switch chips.
No idea what you want to ask here.
*1 - Read some display, even if it's just a few led and inputs - or a keyboard.
*2 - Using the VIC20 as an example is a bit dangerous, as its specific memory decoding is a bit complicated, and its use even more.
*3 - Using a switch instead of grounding would even allow to have two 8 KiB ROM versions online and accessible in a flip of a switch.
And replacing the switches by some latch would make a first step to ROM or more general memory management. But that's a different story.
*4 - To assign the full 16 KiB EEPROM, two 74138 lines need to be joined as CS (chip select). Since they are low active, an AND gate will do the trick.
First note that in "real" retro computers the amount of address lines on a memory chip is generally much lower than the address lines the CPU has. This means that you won't be able to "fill" the CPU's address space without using some more logic, and, obviously, multiple memory chips.
Beyond its address and data lines, every memory chip has some more control lines that define its bus interface and are intended to connect to some address decoding logic.
- /CE - Chip Enable. This is the line that allows the CPU to signal "Yes, I'm talking to YOU" to the memory chip. If this line is not asserted, the chip won't do anything at all, just silently sit on the bus.
- /OE - Output Enable. This line allows the CPU to actually read from the memory chip. When asserted, the memory chip will evaluate the address lines and put the bits addressed by the address lines onto the data bus
- /WE - Write enable. This line, if present (on writable memory), will tell the chip to put the contents of the data lines to the adrerss as signalled
What you see here is the pinout of a 28C16, a 2K x 8 EEPROM. As you can see here, this guy has 11 address lines that connect directly to the CPU's address bus and 8 data lines intended for the data bus. If you connect only those, the chip won't do anything. The important bits are with the /W, /E, and /G lines (/W, /E, and /G are vendor-selected synonyms for the above /WE, /OE, and /CE signals).
/W is the /WE from the explanation above - It tells the chip the CPU wants to write
/E is the /CE from above, enabling the chip ("Yes, I'm talking to YOU")
and /G is the /OE from above, telling the chip to put data on the data bus.
Now let's assume you want to place 2 of these chips into the upper address range of the 6502, the first one covering the address range from 0xF800-0xFFFF, the second one directly below that, from 0xF000-0xF7FF. Obviously, we need to look at the CPU's address lines not connected to the memory, and generate some logic to provide the /CE signals of the chips (/WE and /OE can trivially be connected with some logic to the 6502's R/W signal).
The 5 upper address lines you cannot connect directly to the memory will have a value of 0b11111 for the upper ROM and 0b11110 for the lower one. A circuit like the following would provide the /CE lines for the upper and lower ROM (Note this is non-optimized and very probably non-practical, just explaining the concept):
If you put these two pictures together, you'll end up with a system that has two EEPROMs of 2kBytes each in the upper address space of the 6502.
The most common solution was to have a bank switching register. The register would act like extra address lines, switching RAM and ROM and other chips in and out of the CPU's address space.
Some systems had the bank switch register mapped into memory somewhere, meaning they could only use part of the available address space for switching. Others used extra ports on the CPU designed for this kind of thing, effectively adding an extra bus separate from the main memory one that was used for bank switching and other important functions that the CPU might need to access often.
An example of this is the Commodore 64. It has a 16 bit address space covering 64k, and also 64k of RAM. A bank switch register allows part of that space to be switched between RAM and ROM/video registers.