how do CPU cards work on the Apple II if there's no way to take the bus over?
/DMA (pin 22) is good for. It halts the CPU and tristates the bus. Now any card can take over.
Unlike its daddy, the 6800 (and many other CPUs as well), the 6502 can be halted in at any clock state by pulling
/RDY. It will extend the actual cycle (*1). This doesn't tristate the bus or anything else, and is primarily meant to allow singlestepping and support slow memory, but can do DMA as well. Not very sophisticated, but it does the job.
On the Apple II Woz added a bunch of buffers to tristate the address bus when needed. When DMA gets pulled, the CPU will get its
/RDY pulled and the buffers will tristate the address/data lines.`
Video update and RAM refresh will continue as before - The Card May Only Access the Bus During
Phi0, even with DMA pulled continuous, as video and refresh logic will access the RAM during
But there are Apples fited with a NMOS 6502 (*3). Due its dynamic nature (*4) it needs to do some workout to keep the register content intact. In general, one successful cycle every 10 cycles will do it (*5, 6). Each card needs a appropriate solution.
This can be some counter halting the card every 4th, 8th or 16th cycle and hand one cycle to the 6502, or maybe there are times where the card's CPU doesn't need the bus, which may be always handed over to the 6502 (*7)
The Z80 card is doing the later, as the CPU needs an internal cycle after each opcode fetch (signaled by
M1), where no bus activity happens. relinquishing that to the 6502 makes it happen often enough (*8) without throttling the Z80 at all.
Apple has published a detailed information about DMA handling in their Technical Note Nr.2 for the Apple IIe. While there are some differences with the Apple II, and even more with the IIgs, it does give a good base to understand the workings without traceing schematics.
*1 - Well, it shouldn't be pulled within a write cycle, as the CPU will not repeat such. Then again, when pulled during
Phi1, it will always stop.
*2 - So no, there is no chance to access the RAM at 2 MHz from an I/O card. Would have been nice, wouldn't it?
*3 - so if the card needs only to work with a CMOS like in an enhanced IIe, it will be possible to use all cycles.
*4 - The registers are basically dynamic memory and need refresh.
*5 - It's said that a MOS/Rockwell chip can do 10-17 cycles without, while a Synertec is guaranteed to do 40.
*6 - yes, this means the 6502 is active running at maybe 5-10% speed. So here's your chance for real dual CPU action.
*7 - If these holes are common, the 6502 may get even more usable CPU time.
*8 - Well, going by the books there are some instructions (most notably all modifying with index register + displacement addressing like
RES) which need 23 cycles. Since the Z80 runs at double the 6502 clock (*9), this ends up being 12 cycles, thus still on the good side.
*9 - Well, it's way more complicated than that, but also a great example of clever hardware design. The Z80 runs from the Apples 7 MHz clock, divided by two but only during
Phi1 which will result in a full and a half cycle in the first 6/7th of
Phi1 plus the other half of the second stretching over the rest of
Phi1and all of
Phi0. Effective clock speed is 2.04 MHz, with a non symetric clock (*10). Some instructions are extended by one of the 'short' cycles to synchronize for memory access, making it a little less than 2 MHz in average. Not much.
*10 - Needing a 3.5 MHz Z80 to do so.