What struck me about this image is the amount of empty space!
I have a hard time seeing much empty space here. These are mainly a lot of small areas each defined through the gate structure.
If you look at a modern-day chip, say a Skylake or whatever,
I guess you have some pictures in mind where a whole Skylake is shown about the same size than the 2650. This leads to some easy misconceptions:
Just think of it, the 2650 is what? 10µm or maybe 8µm and is maybe 20mm² big? A 2014 Skylake is more like 14nm and 200+mm². So that's ~10 times the chip size with ~250,000 times smaller gates. So if the picture above is maybe 20cm wide (on your screen or when printed), to get a similar view of Skylark structures, you need to print it out 10,000 cm wide - that's 100m or 300 ft.
Compared it at that scale, you will notice, that 'seemingly' unused areas on a Skylark are way larger than with the 2650 above.
there are not going to be large gaps between the gates.
It's not between, rather within.
It doesn't appear to be for manufacturing reasons;
Well, there are those as well. The main reasons are:
Most importantly, (for small ones) the number of pads. Pads have to have a certain minimum size to make sure the bonding (soldering) machine can put a connection wire without damaging any surrounding structures.
It is a very good idea to reduce corners to a minimum (*1). Each corner does not only introduce noise and reduce speed, but is as well a critical area for etching errors. Less bends mean higher yield.
Then there is signal travel time. in silicon we reach less than half of light speed, on a chip with like 5mm across, a signal already takes about ~7ps to go from one end to the other. Doesn't sound like much, but it adds up when signals have to get routed several times across to pack a structure tighter.
Last but not least, back then most had only two metallic layers (*2). Today, even the cheapest low density processes offer 4 metallic layers, most have 6+ and high end process have 8 or more. It's exactly the same as with PCB design (*3). The more layers, the denser the packaging can be, as less space is required for routing connections (*4).
I guess that's because the traces actually were laid out manually, and arranged neatly.
Neat layouts are usually also the best (*5). It's a situation where our sense for beauty meets with usefulness.
But in the picture below, it looks to me as though they could easily have bunched things up a bit to take less space.
It wouldn't have freed up much space, so no space to squeeze in more functionality.
I believe that would have meant they could fit another few dies on the wafer, increasing yield and decreasing cost.
First of all, that's only a straight payout if increased cost for design, testing and potential higher defects (due more complex structure).
With the above photo it's rather clear that there wouldn't have been much size reduction possible. Even when ignoring the size request for pads, there is in each direction a structure that will need the full height or width. Layout of this structure is defined by it's working, so mirroring it or flipping it to combine 'holes' in one area would result in a greatly increased surface need, as now busses would have to be rerouted. Not to mention speed decrease due a longer signalling path. The 2650 seems to be already a very neat one with its few and clean bus structures.
So what is the reason they used to leave those spaces, and why does that reason not hold now?
Again a misconception. Today, the relative gaps are way larger. Not at least due the use of premade, laid-out blocks. It's just due to the much smaller structures that it doesn't show up as obviously.
*1 - No matter if it's with PCBs or chips - in the latter it's even more important.
*2 - At least in the affordable range.
*3 - after all, the metallic connection layers are the PCB of a chip.
*4 - Which again is a way to achieve (or keep) high speeds, possible because of connections being as direct as possible.
*5 - This does not include such with additions made for beauty. Like everywhere, form follows function - and adding to that will reduce the synergy.