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Here is the Valvo 2650. (Also known by other names, in the UK as Signetics 2650).

What struck me about this image is the amount of empty space! If you look at a modern-day chip, say a Skylake or whatever, there are not going to be large gaps between the gates. The 555 has a lot of space also. I looked at the ARM 1 die, and though not as extreme, I saw similar spaces. It doesn't appear to be for manufacturing reasons; they clearly have a high enough "resolution" (is that the right word) to make intricate structures.

It's more as though the traces were laid out manually, and arranged neatly. I guess that's because the traces actually were laid out manually, and arranged neatly.

But in the picture below, it looks to me as though they could easily have bunched things up a bit to take less space. I believe that would have meant they could fit another few dies on the wafer, increasing yield and decreasing cost.

So what is the reason they used to leave those spaces, and why does that reason not hold now?

Valvo 2650

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    Note with the absence of proper design tools and having to draw a chip manually, it was much more important to create a maintainable design than it is today (where schematic and layout can be created automatically from each other) – tofro Nov 27 '18 at 9:47
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    Also, the outer dimensions was most probably very much defined by the number of pads (and pins). – UncleBod Nov 27 '18 at 10:15
  • @tofro: Indeed, if it turns out that a design needs to be adjusted, anything between the point of adjustment and the nearest bit of open space might need to get pushed around. Having lots of small bits of open space available can make modifications much easier. – supercat Nov 27 '18 at 18:16
  • Are sure this is a 2650? The die shot looks very different to the ones on wikipedia. It's supposed to have a ROM section that I can't see. – PeterI Nov 28 '18 at 0:17
  • @PeterI Oh you're (half) right, it's not the original Signetics part, but a licensed copy by Synertek. This picture is right there on Wikipedia, under the heading Second sources. – Wilson Nov 28 '18 at 8:34
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What struck me about this image is the amount of empty space!

I have a hard time seeing much empty space here. These are mainly a lot of small areas each defined through the gate structure.

If you look at a modern-day chip, say a Skylake or whatever,

I guess you have some pictures in mind where a whole Skylake is shown about the same size than the 2650. This leads to some easy misconceptions:

Just think of it, the 2650 is what? 10µm or maybe 8µm and is maybe 20mm² big? A 2014 Skylake is more like 14nm and 200+mm². So that's ~10 times the chip size with ~250,000 times smaller gates. So if the picture above is maybe 20cm wide (on your screen or when printed), to get a similar view of Skylark structures, you need to print it out 10,000 cm wide - that's 100m or 300 ft.

Compared it at that scale, you will notice, that 'seemingly' unused areas on a Skylark are way larger than with the 2650 above.

there are not going to be large gaps between the gates.

It's not between, rather within.

It doesn't appear to be for manufacturing reasons;

Well, there are those as well. The main reasons are:

  • Most importantly, (for small ones) the number of pads. Pads have to have a certain minimum size to make sure the bonding (soldering) machine can put a connection wire without damaging any surrounding structures.

  • It is a very good idea to reduce corners to a minimum (*1). Each corner does not only introduce noise and reduce speed, but is as well a critical area for etching errors. Less bends mean higher yield.

  • Then there is signal travel time. in silicon we reach less than half of light speed, on a chip with like 5mm across, a signal already takes about ~7ps to go from one end to the other. Doesn't sound like much, but it adds up when signals have to get routed several times across to pack a structure tighter.

  • Last but not least, back then most had only two metallic layers (*2). Today, even the cheapest low density processes offer 4 metallic layers, most have 6+ and high end process have 8 or more. It's exactly the same as with PCB design (*3). The more layers, the denser the packaging can be, as less space is required for routing connections (*4).

I guess that's because the traces actually were laid out manually, and arranged neatly.

Neat layouts are usually also the best (*5). It's a situation where our sense for beauty meets with usefulness.

But in the picture below, it looks to me as though they could easily have bunched things up a bit to take less space.

It wouldn't have freed up much space, so no space to squeeze in more functionality.

I believe that would have meant they could fit another few dies on the wafer, increasing yield and decreasing cost.

First of all, that's only a straight payout if increased cost for design, testing and potential higher defects (due more complex structure).

With the above photo it's rather clear that there wouldn't have been much size reduction possible. Even when ignoring the size request for pads, there is in each direction a structure that will need the full height or width. Layout of this structure is defined by it's working, so mirroring it or flipping it to combine 'holes' in one area would result in a greatly increased surface need, as now busses would have to be rerouted. Not to mention speed decrease due a longer signalling path. The 2650 seems to be already a very neat one with its few and clean bus structures.

So what is the reason they used to leave those spaces, and why does that reason not hold now?

Again a misconception. Today, the relative gaps are way larger. Not at least due the use of premade, laid-out blocks. It's just due to the much smaller structures that it doesn't show up as obviously.


*1 - No matter if it's with PCBs or chips - in the latter it's even more important.

*2 - At least in the affordable range.

*3 - after all, the metallic connection layers are the PCB of a chip.

*4 - Which again is a way to achieve (or keep) high speeds, possible because of connections being as direct as possible.

*5 - This does not include such with additions made for beauty. Like everywhere, form follows function - and adding to that will reduce the synergy.

  • @TobySpeight ROTFL ... oh gawd. You are right. And you're the first to correct me. In all the years (it's like 4, isn't it) I have read 'Skylark' And I guess even said so. Except, that's a plane, not a CPU ... one should not mix up hobbies. Thanks – Raffzahn Nov 27 '18 at 16:09
  • Also, two conductors closer together create more capacitance, which slows signal propagation and increases energy use. – Warren Young Nov 28 '18 at 17:17
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    I tried to fix your "Skylark" references, but the site wouldn't let me make such tiny changes. – Warren Young Nov 28 '18 at 17:17
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Chips of that era were done by hand layout, typically colored pencil on mylar. Hand layout is not automatic, and thus not fast, neither completely predictable in die area in advance. Portions of a layout might be done by different people at different times and/or with different skill levels.

Floor planning was done before layout, and was thus based on estimates of the various sub-block sizes, so some breathing room might be left to be conservative about how well the layout specialist might be able to fit their sub-block into the layout. Sub-blocks might also have been allocated to layout in nice rectangles, even though those rectangles might not pack at maximum efficiency in the final die size.

Thus, even high volume consumer chips might end up with gaps between blocks, or even large holes in the middle of a layout, especially when a layout specialist exceeded her/his budgeted component density.

There may also be reasons to be conservative about density at the planning stage for reasons of thermal spreading, capacitive coupling, package pinout limitations, and etc.

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