The ZX Spectrum (and therefore the Harlequin) has its ROM from $0000 to $3FFF, while RAM further up to $5AFF is used for the screen (see Memory-Map). As CP/M expects RAM from $0000 upwards the two are incompatable by default, but CP/M is available for the ZX Spectrum +3.

How might it be possible to easily modify a Harlequin to add RAM paging so CP/M could run?

Maybe with a Beta 128 disk interface?

3 Answers 3


The latest version of the "Superfo Harlequin 128 (issue 4)" supports ALLRAM mode


You can connect a floppy disk interface and run CP/M 2.2 or CP/M Plus, the same as a ZX Spectrum +3

  • 2
    Mind to turn this into a full answer, otherwise it's at best a link only comment to this answer. If not an (even less well received) advertisement?
    – Raffzahn
    Dec 3, 2020 at 1:42

well even old ZX 48K and clones have exposed the AD/DB/CB buses along with /ROMCS signal which can actively disable inbuild ROM. So you can make a small HW that has 16 KByte of SRAM that replaces the ROM with a jumper or switch or programaticaly using some flip/flop and address decoder.

This technique is used by any HW peripherial with its own ROM for example like this:

Developing such HW should be quite easy for anyone with the EE knowledge as its really just a connection between BUSes and the IC. I would also add some LED indicating the state of /ROMCS

However I think there should be some HW peripherial capable of this already out there so just look may be some DivIDE or MMC card interface for ZX ...

I am not familiar with CP/M (other than that it requires 64 KByte of RAM in full AB range which actively mess up running its stuff on ZX and need some porting) but I think it would need some tweaking or adding driver for the display as there is not much options to move the SCREEN file from its location.

For example here schematic for D40 taken from mts.speccy.cz

D40 MDOS 1.0

The IC11 (27128) is the EPROM mapped instead of ZX original ROM The CE chip enable signal is connected to the adress decoder (that is active in address range <0-16383>) The /RD is connected to Z80 CPU /RD and you woul dneed just replace EPROM with SRAM and also connect the /WR signal.

The only thing left to see in the circuit is the /ROMCS on the image is called ROMOFF on the image its the open collector of transistor T1 just above the EPROM (the text is not recognizable but I am confirming this with my own paper version of the circuit)

so in the nutshell I see it like this:

full RAM mode

Where jp1 will switch between FULL RAM mode and normal ZX ROM operation. If you want to switch programatically then remove the jumper and add a flip flop + I/O space address decoder instead of it.

I assume you want to load some stuff like OS into some memory first (using in build ZX ROM), than switch to FULL RAM and move the OS to desired locations and run it. So you would also need to write a small probably assembly loader that do this for you.

[Edit 1] I just found this:

Which looks like contain ROM file,CP/M 2.2 TZX file and PDF with description and Schematics for the RAM extention which more or less covers this answer fully.

  • Interesting. Maybe something like the pagable ROM module from the RC2014 could be used Dec 21, 2018 at 11:02
  • @PaulHumphreys yes the design is almost what you need ... you just need to switch the (E/E/P/)ROM with SRAM and also add /WR signal connection. But as you cas see its just connector + ROM/RAM + address decoder + flip/flop/latch for activation. However the variable page size a bit complicates the decoder ... What you need could be a bit easier
    – Spektre
    Dec 21, 2018 at 13:07
  • @PaulHumphreys just to be sure I added edit to my answer with some circuitry ...
    – Spektre
    Dec 21, 2018 at 13:59
  • Even if you paged RAM into the bottom 16k, a 48k Spectrum wouldn't be suitable for CP/M because of the video RAM at 0x4000. On a 128 things are better because the second screen in bank 7 can be used, and paged in and out as required.
    – john_e
    Dec 22, 2018 at 0:18
  • @john_e I was afraid of that (and mention exactly this same in the answer just above the circuitry of the D40/D80) ... however I saw programs ported from CP/M to ZX like ZEXALL and they works ... maybe adding some driver would enable the ZX48k for CP/M too (like allocate the SCREEN FILE location to prevent OS to use it) but still this approach should be usable even for 128K and later models
    – Spektre
    Dec 22, 2018 at 7:40

The hardware modifications are possible, and actually already done. The "SuperFoo Harlequin 128" is an all-RAM design based on the original Harlequin that should be capable of running CP/M (Just like the +2 and +3).

I haven't heard of someone actually running CP/M on such a machine, but based on its +3 compatibility, it shouldn't be too hard. Some of the boards based on this design come with a built-in DIVMMC - See my question here (that is unfortunately still missing a definitive answer) related to this and CP/M.

  • Doesn't the superfo harlequin only support the 128k memory mapping though? The +3 had a new memory mapping setting just to support CP/M worldofspectrum.org/faq/reference/128kreference.htm Dec 19, 2018 at 22:58
  • @PaulHumphreys The Harlequin 128 with superfoo mods runs the +3 ROM, so I would expect it uses the same (all-RAM) memory layout.
    – tofro
    Dec 19, 2018 at 23:02
  • The zip file containing the 128K mods shows it running the 128k ROM and not the +3 one and the screenshots only show the 128k mode being tested and not the all RAM mode unique to the +3 and some +2s. In addition, the .txt file in the superfo docs says "For 128K, signal 1FFD is not used.". Port 0x1FFD is needed to switch to all RAM mode. I do notice the superfo design uses 2 128k ram chips. Does the superfo have some other means of switching to all ram perhaps? Dec 19, 2018 at 23:17
  • Mine runs the +3 ROM. I have a Chinese re-make (ZX Omni). On second thought, I am, however, not 100% sure if the +3 ROM ever switches into all-RAM mode.
    – tofro
    Dec 19, 2018 at 23:19
  • 1
    If you have a 128k harlequin, would you be able to test whether the all ram mode is accessible somehow and report back? Dec 19, 2018 at 23:41

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