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The ZX Spectrum (and therefore the Harlequin) has its ROM from $0000 to $3FFF, while RAM further up to $5AFF is used for the screen (see Memory-Map). As CP/M expects RAM from $0000 upwards the two are incompatable by default, but CP/M is available for the ZX Spectrum +3.
How might it be possible to easily modify a Harlequin to add RAM paging so CP/M could run?
Maybe with a Beta 128 disk interface?
The latest version of the "Superfo Harlequin 128 (issue 4)" supports ALLRAM mode
https://onedrive.live.com/?id=E0ADBB58ADB8D869%21209864&cid=E0ADBB58ADB8D869
You can connect a floppy disk interface and run CP/M 2.2 or CP/M Plus, the same as a ZX Spectrum +3
well even old ZX 48K and clones have exposed the AD/DB/CB buses along with /ROMCS signal which can actively disable inbuild ROM. So you can make a small HW that has 16 KByte of SRAM that replaces the ROM with a jumper or switch or programaticaly using some flip/flop and address decoder.
This technique is used by any HW peripherial with its own ROM for example like this:
Developing such HW should be quite easy for anyone with the EE knowledge as its really just a connection between BUSes and the IC. I would also add some LED indicating the state of /ROMCS
However I think there should be some HW peripherial capable of this already out there so just look may be some DivIDE or MMC card interface for ZX ...
I am not familiar with CP/M (other than that it requires 64 KByte of RAM in full AB range which actively mess up running its stuff on ZX and need some porting) but I think it would need some tweaking or adding driver for the display as there is not much options to move the SCREEN file from its location.
For example here schematic for D40 taken from mts.speccy.cz
The IC11 (27128) is the EPROM mapped instead of ZX original ROM The CE chip enable signal is connected to the adress decoder (that is active in address range <0-16383>) The /RD is connected to Z80 CPU /RD and you woul dneed just replace EPROM with SRAM and also connect the /WR signal.
The only thing left to see in the circuit is the /ROMCS on the image is called ROMOFF on the image its the open collector of transistor T1 just above the EPROM (the text is not recognizable but I am confirming this with my own paper version of the circuit)
so in the nutshell I see it like this:
Where jp1 will switch between FULL RAM mode and normal ZX ROM operation. If you want to switch programatically then remove the jumper and add a flip flop + I/O space address decoder instead of it.
I assume you want to load some stuff like OS into some memory first (using in build ZX ROM), than switch to FULL RAM and move the OS to desired locations and run it. So you would also need to write a small probably assembly loader that do this for you.
[Edit 1] I just found this:
Which looks like contain ROM file,CP/M 2.2 TZX file and PDF with description and Schematics for the RAM extention which more or less covers this answer fully.
/WR signal connection. But as you cas see its just connector + ROM/RAM + address decoder + flip/flop/latch for activation. However the variable page size a bit complicates the decoder ... What you need could be a bit easier
The hardware modifications are possible, and actually already done. The "SuperFoo Harlequin 128" is an all-RAM design based on the original Harlequin that should be capable of running CP/M (Just like the +2 and +3).
I haven't heard of someone actually running CP/M on such a machine, but based on its +3 compatibility, it shouldn't be too hard. Some of the boards based on this design come with a built-in DIVMMC - See my question here (that is unfortunately still missing a definitive answer) related to this and CP/M.
