In the Block Diagram the Stack Pointer Register (S) has a HOLD command in addition to the LOAD and BUS ENABLE commands. The HOLD command is linked to the S/S output of the Random Control Logic. What is the purpose of that line ?
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I would not trust much reverse engineered stuf as it might be different than the real deal but this: www.visual6502.org is based on actual die simulation from image so its almost the real deal... so run the simulation and trace your signal in question ...– SpektreDec 21, 2018 at 9:02
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It might help to understand how/where the increment/decrement happens for the Stack Pointer Register. Does it happen within the S register block, like the PC (PCL/PCH), or is the S register value shipped to the main ALU and then sent back after adjustment? (If the former, there has to be some way to signal when to inc vs. dec vs. neither, and if the latter, it is at least 2 cycles that would be coordinated by random control logic.)– Erik EidtDec 24, 2018 at 15:54
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1 Answer
A few years ago there was a reverse-engineered schematic of the 6502 available in the internet which shows the single transistors. (Maybe it is still available now.)
Back then I had downloaded that schematic so I could compare the "S" register to the "X" and "Y" registers right now:
"S" has three input lines (named "x1" to "x3" in the reverse-engineered schematic) while "X" and "Y" have two input lines ("x4" and "x5" respectively "x6" and "x7").
This makes me think that the block diagram is not correct because "hold", "load" and 2x"bus enable" are four inputs while there are only three inputs in the schematic.
There are more oddities in the block diagram...
So I simply assume that this diagram is not correct.
answered Dec 21, 2018 at 8:29
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1Maybe you can pinpoint it in visual6502 instead of the single-transistor diagram?– dirktDec 21, 2018 at 10:21
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True, Hansons diagram is quite helpful, but not in all details complete.– RaffzahnDec 22, 2018 at 1:09
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