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Back in the days of Parallel ATA (a.k.a. IDE) it was possible to connect two drives with a single cable. The ATA standard defines a number of modes with different speeds which the drives and the controller use to communicate over the ATA cable. Controllers could support a feature called "independent device timing" to allow each drive to communicate at its fastest speed, instead of both drives being slowed down to the speed of the slowest drive. How did that work at the electrical and protocol level?

Naively I would think that the slower drive would get confused by the higher clock speed data transfer for the faster drive, and if not locking up outright it would not be able to detect when the transfer for the fast drive would be finished and so when it could expect a next transaction directed at itself. But apparently that didn't happen, so how was independent device timing implemented?

edit: clarify I'm talking about ATA interface transmission speed, not the drive's own read/write speed

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    Are you sure this is a thing at all? Maybe some source for your claim about slowing down, clock or whatsoever?
    – Raffzahn
    Dec 28, 2018 at 19:52
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    The main reference on the internet for independent device timing seems to be pcguide.com/ref/hdd/if/ide/confTiming-c.html. Different UDMA modes use lower cycle times/higher frequencies, so somehow devices only supporting a lower UDMA mode are not getting confused by higher UDMA mode transfers to the other drive on the cable. If you feed any random digital device data at a speed it was not designed for it is not going to work, but in some way it does work for IDE drives.
    – JanKanis
    Dec 28, 2018 at 20:04
  • Could it be that you miss the fact, that IDE is not a drive interface, but a subset of the AT ISA bus? There is no direct interaction with a drive, but simple I/O operations on the ISA bus. UDMA is just a speed up to the memory cycle used over this interface (after being detatched form the original bus interface due later development). Threse are two different issues.
    – Raffzahn
    Dec 28, 2018 at 20:11
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    There are several ways this could work, but I can't find any definitive answer on if one of these is correct. Maybe the control messages are at the slower speed and only the DMA transfer is at the faster speed, and so the slower device knows for how long to ignore the bus. Maybe the standard defines that devices should be resistant to higher speed signals they can't interpret. Maybe something else still.
    – JanKanis
    Dec 28, 2018 at 20:17
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    IIRC each drive has its own select line like a chip select on IC and has jumpers to select one. So the interface can ignore any stuff not belonging to it no matter the clock speed ... so I see no problem implementing such behavior like you ask about electricaly
    – Spektre
    Dec 29, 2018 at 9:58

1 Answer 1

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I think I found the main part of the answer by searching through a standards document.

IDE connectors have some dedicated and re-purposed signal lines specifically for DMA. Some of these stay asserted for as long as a DMA transfer is in progress, allowing the other device to see when a DMA has finished and thus when new commands can be sent by the host. [1] I saw somewhere that DMA cannot be used if the other device on the cable does not support at least some DMA mode (so that it understands the meaning of the control signals), but I cannot find the reference back.

For sending commands there are similar signal lines that indicate if a command is in progress or if the command is done. When writing the command there are dedicated signal lines that indicates the target device and register. Writing a command is limited to the speed of the slowest device, writing data can be done at the target device speed as long as the device selection and register signal lines don't change. [2]

[1]: The ATA standard ("Information Technology - AT Attachment with Packet Interface – 7 Volume 2") of which I found a draft here; section 8: Parallel interface signal assignments and descriptions, 8.1, 8.2 (p 61-63).

[2]: idem section 12.2: transfer timing. Table "Register transfer to/from device" note 4 (p 148):

Mode shall be selected no higher than the highest mode supported by the slowest device.

Table "PIO data transfer to/from device" note 4 (p150):

Mode may be selected at the highest mode for the device if CS(1:0) and DA(2:0) do not change between read or write cycles or selected at the highest mode supported by the slowest device if CS(1:0) or DA(2:0) do change between read or write cycles.

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