I'm not sure I've entirely formed the idea in my head, but I'll ask anyway...

One of the things I learned here in RO is that the BBC gained speed by using faster RAM, thereby avoiding cycle stealing during video refresh. IIRC, this resulted in ~30% better performance.

My question is whether it would be possible to get the same performance boost using solutions that were available earlier and were cost effective at that time, that is, the ~1981 time frame.

  • I assume dual-ported RAM would allow this, but was this widely available and cost competitive? Could one have a small section of dual-port and then a larger bank of "normal" RAM without issue?

  • could one mix high- and low-speed parts on a single bus? Do the refresh requirements change as well, and would that preclude such solutions?

  • something else I haven't thought of?

  • I'm not realy sre if I understand what you mean with 'gained speed' and '30% better' (compared to what). In general: a) yes, no, yes; b) yes,(usually) no; c) Hard to answer, since I don't know you think :)). In general any addition of faster/slower memory will result in additional circuitry to either slow the CPU or decouple the memory for some time from the CPU, making it (usually way) more expensive than without.
    – Raffzahn
    Jan 11, 2019 at 17:04
  • Gained speed in that the BBC could run a program 30% faster than an Atari in spite of the same CPU speed because the Atari was waiting on ANTIC access while the BBC interleaved accesses due tof atser RAM. Jan 11, 2019 at 17:23
  • They utilized differnt clocks to start with, the BBC being already about 10% faster clockwise - then it's BASIC was way more speedy (Atari BASIC sucked). So what are the numbers to state a 30% higher speed. It would be great if you could elaborate the base for the 30% in a consistent fashion - otherwise it's hard to give a useful answer.
    – Raffzahn
    Jan 11, 2019 at 17:59
  • I finally understoof that RO is meant to say RC :)) So if you learned this here, could you maybe point out the related questions as reference? I couldn't come up with a relevant selection when searching.
    – Raffzahn
    Jan 11, 2019 at 18:01
  • 2
    Dual-ported RAM was available in 1980 and would have been competetively priced - Competitively to other dual-ported RAM, but way more expensive than "normal" RAM. Which is still the case today. DP-RAM was always only available as SRAM, which has per se a much higher price than DRAM, and dual-ported can easily be 10 times more expensive than normal SRAM. (example prices: 8k x 8 today SRAM: €2,50, DP-SRAM 23€.)
    – tofro
    Jan 11, 2019 at 18:26

2 Answers 2


As to the headline question: yes.

The Acorn Electron, a convenient example because it's a BBC relative, proves this after a fashion. ROM is accessed at 2Mhz. The supplied RAM, which is shared with video, is accessed at at most 1Mhz. This is effected by slowing the CPU's clock based on its access destination.

A modification to the machine was to replace the low 8kb of address space with RAM that didn't sit behind the ULA. So it was no longer available for video but could now be written to and read by the CPU at 2Mhz.

So at that point you had a 6502 that didn't just access some areas of memory more quickly than others, but used two observably different speeds of RAM in the same machine.

Re: refresh, that counteracts leakage. So refreshes must occur within an absolute amount of real-world time. It's independent of the access speed the RAM is being used at.

Otherwise, the 6502's fixed memory access cadence obviated any need for dual-port RAM in its class of machines. It was always the case that you'd see half a cycle in which the 6502 was bus master and then half a cycle in which it wasn't. So the best solution for frictionless dual access on a 6502 machine is just to have video control the bus every other half cycle.

The BBC does this, as did the Apple II a few years before, and later machines like the Oric. Where bandwidth was insufficient with that access pattern, doing what approximately amounts to using a 16-bit bus for graphics fetching was an option: that's what the Apple IIe does in 80-column mode. Within each video access window it simultaneously fetches bytes from two physically different 8-bit portions of memory.

  • Excellent answer, precisely what I was curious about. It is precisely the timing of the half-cycle that I was curious about. Machines like the Apple II and Atari lost considerable performance waiting on the bus, which could be addressed with faster RAM, but at a cost. So my question is whether it's possible to replace SOME of the RAM with faster bits to avoid this contention while not having to do it all and thus drive up costs. This answer clears says "yes". Jan 15, 2019 at 19:06
  • I don't get what you're talking about. Are you meaning was it done in the past, or do you mean in a new design today? Or do you mean could things have been done differently in the past than they were?
    – Robotbugs
    May 28, 2019 at 9:16
  • You can read great depth about the Apple II on this subject here: mirrors.apple2.org.za/Apple%20II%20Documentation%20Project/…
    – Robotbugs
    May 28, 2019 at 9:19
  • 1
    I'm curious why the 6502 made RDY responsive on all read accesses, rather than just opcode fetches, but not on write accesses. When running at 1MHz, the 6502 could tolerate up to 10 missing clock pulses without difficulty, and while being able to stalling the processor indefinitely is useful, I don't see a particular planned benefit to delaying operand reads by more than ten cycles without being able to do likewise for writes. Something like the VIC-II chip may have been simplified slightly by the ability to stall the CPU for 40 cycles after a 3-cycle delay, but...
    – supercat
    May 28, 2019 at 15:22
  • ...of course the VIC-II wasn't on the radar when the 6502 was being designed. Further, being able to delay individual cycles would seem like it would allow for more interesting design options than having to do have each group of cycles preceded by a 3-cycle delay.
    – supercat
    May 28, 2019 at 15:28

The 6502 was intended to be run a constant clock rate and the early version were 1MHz but later 2MHz and higher. Also some of the peripheral chips became faster with time but not all of the useful ones.

With 1MHz you can put any speed of RAM or ROM in there as long as it meets the setup times for read and write for the CPU. I can put a modern 10ns static RAM in a 1MHz system typically without problem but it's not going to run faster unless the system clocking is increased.

But in the late 80s they started to use some faster chips and the 2MHz 6502B and switch clocking rate dynamically between 1MHz and 2MHz depending on the address accessed, so that slower chips could also be used. You see that in the BBC Micro computer model B. The clock changing circuitry is a bit of a *** to understand because ideally the 6502 is supposed to be outputting two non-overlapping clock waveforms 01 and 02 from the input clock and I think changing the clock rate was a bit difficult without glitches. In the BBC Micro it gets stretched by half cycles to slow down rather than just going directly from 2MHz to 1MHz. It might seem the same but you have to check the circuitry which is right in the middle: http://www.goffart.co.uk/museum/schematics/bbc_b.pdf

You can see on the schematic that it has address decoding from IC24 (LS138) through to the inverter of IC33 (LS04) and that's what triggers the clock to slow down from 2MHz to 1MHz, but it's quite complicated because the circuit with all the flip flops depends on the 01 output of the 6502 as well as the clock counter chain input.

I don't think any machine from the era can detect magically how fast the memory is and speed up or slow down, and especially using the 6502 which doesn't have a very good wait system to insert cycles anyway. It has RDY, but it's rather cumbersome.

The BBC has fairly fast dynamic RAM which is refreshed by video access. Typically the video chip is accessing every RAM row so nothing else is needed for refresh. The CPU would access the RAM transparently on every half cycle so there's no such thing as stealing access from the video system. They're accessing memory in alternation. That's what many home computers did at that time.

Also DRAMs at that time were not that critical with refresh. You can stop refreshing them for a few seconds with hardly any data corruption. That's from personal experience with 4164 and other DRAMs. The charge leaks away over a few seconds.

In the BBC schematic IC45 is selecting the row and column addresses for the RAM in a cycle so it alternates between video and CPU access: the LS139 chip's B input is connected to the 2MHz clock so the RAM address source selecting is done based on the clock state so the CPU is getting the RAM for half the time.

Back in the 80s dual-port RAMs were like 256 bytes, and really freaking expensive.

  • "The 6502 was intended to be run a constant clock rate" Glad noone told this to Woz when designing the Apple II :)
    – Raffzahn
    May 28, 2019 at 10:13
  • "You see that in the BBC Micro computer model B" I'm pretty sure you see that in all variants of the 8 bit BBC micro, not just the model B. May 28, 2019 at 15:38
  • So I thought that the BBC was running 2 MHz the whole time, but it appears that is wrong. But why is this? If the RAM is fast enough, what's the purpose of lowering the CPU speed? Was this for particular video modes perhaps? May 28, 2019 at 21:54
  • @Raffzahn: Are you talking about the fact that every 65th cycle is 14% longer than the rest, or something else?
    – supercat
    Dec 24, 2021 at 19:19
  • @supercat For the Apple II? Yes, exactly that, it varies the clock frequency for that cycle. Point is, the 6502 (and any other) CPU is not per se made for constant clock as the answer states, but to run within the timing parameters set. An frequency and any mixture of frequencies within these boundaries are fine.
    – Raffzahn
    Dec 24, 2021 at 19:45

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