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In the BESM-6, there is an instruction (045) to add index registers, but not to subtract them, however, there is a nearby unused opcode 047, which is made synonymous to 045 (in fairness, that's true only in the kernel mode; in the user mode it traps as illegal).

Also, there are "branch if index is zero" (34) and "branch if index is not zero" (35), but not "branch if index is less than zero" (alternatively formulated as "branch if the MSB of the index is set"). However, there is a nearby unused opcode 36 which is made completely synonymous to 34.

This makes one to think that the unimplemented functionality was intended by the initial design (no references to confirm or deny it, unfortunately), but didn't make it into the hardware for one reason or another, be it physical space constraints, timing requirements, etc.

Are there any similar Western examples of an instruction set with obviously cut corners, or is this kind of mishap specific to socialist economy?

An answer could be in the form "Here's the instruction set of CPU X with an instruction with opcode A doing foo, but no instruction to do bar, which would be obvious to include for completeness/orthogonality; at the same time there is an unused opcode B close to A".

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    I'm tempted to vote for closing this, as answers can only be opinions. After all, as soon as a machine is Turing complete, it can produce any desired output, having more instructions just simplifies individual aspects. Most obvious with the branch example given, as both existing jumps can easy be used to synthesize the third.
    – Raffzahn
    Feb 1, 2019 at 18:55
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    @Raffzahn No, not so easy. Try writing a "branch if negative" using only moves, additions, and branches if zero/non-zero in any architecture.
    – Leo B.
    Feb 1, 2019 at 19:00
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    @LeoB. Well, the first question would be about the index registers being signed values at all - are they? Not clear from the Page linked, so are they? If not, any test for negative doesn't make sense.
    – Raffzahn
    Feb 1, 2019 at 19:22
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    @Raffzahn Given that the addition operation is 2's complement, a bit vector can be looked at as signed or unsigned arbitrarily.
    – Leo B.
    Feb 1, 2019 at 19:28
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    The Data General Nova had Boolean AND but no Boolean OR. You could get around this with De Morgan's laws, but it seems like a fundamental instruction to omit.
    – Ken Shirriff
    Mar 12, 2019 at 22:53

6 Answers 6

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Are there any similar Western examples of an instruction set with obviously cut corners

Following on your example of having addition but not subtraction, the Intel 8080 has 8 bit addition and subtraction instructions laid out neatly as you can see in this table on rows 8x and 9x.

The 8080 also has a 16 bit addition instruction DAD with opcode 0x09, but there is no 16 bit subtraction. The logical place for it in the opcode table would be one column left at 0x08, but that is a NOP on the 8080. Most of the hardware necessary for subtraction is on the die. It just wasn't implemented for some reason.

On the 8085 there's even an undocumented opcode that does implement 16 bit subtraction at 0x08. Though unlike the 16 bit addition, it doesn't update the flags properly, which I suspect is why it's undocumented. You can find a table of the 8085 opcodes here.

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    @Raffzahn Yes, absolutely. Subtraction is less important to have since it can be synthesized. With pointers, a good assembler will handle negative constants so you can just do something like DAD -2 (0xFFFE) if you want to subtract 2. Subtraction at run time would however require generating the 2's complement of the subtrahend first, or chaining 8-bit subtractions.
    – RETRAC
    Feb 1, 2019 at 20:49
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    @Raffzahn Prove - no, but aliasing opcodes instead of making the extra one a no-op or an illegal instruction is unusual enough to raise suspicion.
    – Leo B.
    Feb 1, 2019 at 20:59
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    @LeoB. The BESM-6 is far from the only processor which doesn't bother to fully decode its instructions. The original NMOS 6502 was a minimal design, and they did not bother to fully decode the opcode space to turn unimplemented opcodes into NOPs. The opcodes in question behaved in a variety of ways: some would crash the processor, some behaved unreliably, some were useless for programming, and a few actually turned out to be useful by accident. This was certainly an intentional design choice to save die area.
    – RETRAC
    Feb 1, 2019 at 21:12
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    @LeoB. It's a mix of both. Based on the encoding of the CMP instruction, one might expect CPX with Y-indexed absolute addressing with opcode F8, but that sets decimal mode. On the other hand, ASL (arithmetic shift left) with the encoding specifying an immediate simply crashes the processor and requires a reset.
    – RETRAC
    Feb 1, 2019 at 21:47
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    @RETRAC: More interestingly, the 6502 lacks an opcode for LDX (zp),y but an undocumented opcode will behave like a simultaneous LDA (zp),y and LDX (zp),y. Likewise, it lacks DEC (zp),y but includes an opcode that behaves like a simultaneous DEC (zp),y and a CMP with the value that results from the DEC.
    – supercat
    Mar 24, 2021 at 19:12
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The 6502, released in 1975, had a missing instruction when first released: it had a ROL (ROtate bits Left) instruction, but no corresponding ROR (ROtate bits Right) instruction. This was reputed to have been because a bug was found in the circuit for the ROR instruction, but this has since been disproven by analysis of original 6502 dies: there's no evidence of the faulty/disabled instruction on the die; it was just never included.

While the ROR instruction was absent at first (as seen in the 1975 datasheet,page 6), it was soon added in a hardware revision, and the ROR instruction was included from the 1976 datasheet (page 5) onward.

Some versions of Microsoft BASIC for 6502 machines had workarounds in their floating point instructions to avoid using the ROR instruction. See https://www.pagetable.com/?p=45 for an example.

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  • Unlike 6502, the IC version of the BESM-6 CPU released more than a decade later, hasn't implemented the missing instructions, probably to avoid breaking code compatibility at the user level.
    – Leo B.
    Feb 5, 2019 at 1:08
  • @OmarL Agreed, hence I described it as such in my answer. But you could argue that it was blatantly missing (from the programmer's point of view) in the initial release.
    – Kaz
    Mar 25, 2021 at 13:46
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    The instructions INA and DEA were blatantly missing from the original 6502 IMO (and deliberately so). See also retrocomputing.stackexchange.com/questions/13023/…
    – JeremyP
    Mar 26, 2021 at 10:27
  • Actually seems unusual for that era to keep the same part number and change something significant, and/or create a datasheet that is incompatible with some parts bearing that number...
    – rackandboneman
    Sep 29, 2021 at 22:03
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    You may be interested to know that this myth has been busted! For those who aren't going to watch the video, it is not a buggy ROR instruction, it's a missing feature. They didn't put in the ROR instruction until Revision D. That means that this answer actually does answer Leo B's question.
    – Omar and Lorraine
    Sep 7 at 15:34
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Socialism is terrible - but there are other reasons for "cut corners" leading to missing instructions. For example, capitalism.

In the minicomputer era it was reasonably common for there two be two variants of a machine: one without floating point and one with. You paid more $$$$ for the one with.

I'm thinking specifically of the Honeywell 716 - but there were several others. One interesting thing about the 716: It wasn't a matter of the expense of the parts. The only motherboard had the parts. The difference between the 716 without FP and the 716 with FP was that to add FP you cut a trace on the motherboard.

(The general customer didn't know this of course. I know it because I worked for a Honeywell division that saved money by buying 716s without and using a xacto knife to turn them into 716s with.)

This isn't quite the same, to my mind, as whether you had a FP coprocessor or not, for machines that did that, as in the 8086/8087. I mean, it is sort of. But, it also isn't sort of. (Maybe someone can help me clarify this thought...)

(You can also quibble if you wish that this doesn't really answer the OP' question. Maybe not. But where else could I explain this?)

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    Sort of like a Tesla with a battery software locked to less than full power.
    – manassehkatz-Moving 2 Codidact
    Feb 6, 2019 at 2:22
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    @manassehkatz - Well, that's another story! Amdahl used to sell an IBM 360/370 compatible - forget the model number - that had a "turbo" switch on the front. (Forget the marketing name for it.) Most of the month you had something like a machine comparable to an IBM 370/148 or so, and that's what you were paying for. But, you know how you have that processing crunch at the end of the month to 'close the books'? You flipped the switch, or turned the dial, and instantly you had 20% more oomph. And you paid for that boost, on a meter, for a couple of days each month. First overclocking!
    – davidbak
    Feb 6, 2019 at 2:35
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    That's not "blatantly missing", that's "deliberately put behind a paywall". :)
    – Leo B.
    Feb 6, 2019 at 18:05
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    That's still the practice at Intel. All the features like ECC memory, transaction, hyperthreading instructions are lasered off to put in the different categories of i3,i5,i7 or i.
    – Patrick Schlüter
    Mar 25, 2021 at 15:22
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    @PatrickSchlüter however, this could also very well be a way to reuse dies where these features are defective in the first place.
    – rackandboneman
    Apr 3, 2021 at 19:07
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The Manchester 'Baby' famously had neither 'load accumulator with value from memory' nor 'add value from memory to accumulator'.

Rather, it had 'load negative' and 'subtract'. Nevertheless, these were sufficient to allow programs to be written, and in fact the Baby was the first operational stored-program digital computer.

The lack of ability to do any arithmetic other than negate or subtract was a consequence of its intent as a device for evaluating Williams Tube memory.

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Fairchild F8

There is "add to accumulator" but no subtract.

There is "decrement register" but no "increment register"

There is "increment accumulator" but no "decrement accumulator"

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    What are the codepoints for these instructions?
    – Omar and Lorraine
    Mar 25, 2021 at 10:29
  • It was deliberate choices, most opcodes are used. It's just a very weird CPU.
    – TEMLIB
    Mar 25, 2021 at 11:49
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    @TEMLIB Then they were not "blatantly missing" but rather "deliberately omitted".
    – Leo B.
    Mar 25, 2021 at 19:00
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I'm surprised no one has brought up the System/360 Model 20 yet, a cost and instruction set reduced version of the /360 architecture.

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    Maybe because it's not 'missing' instructions? The -20 is a 16 bit version of the basic /360 without FP, supervisor mode, no I/O processor and halve the registers. It includes all (16 bit) binary instructions, all BCD, all logical instructions and all addressing modes, but restricted to 16 bit words. There was nothing missing. In fact, up to ca. 1982 we operated several application using the same code base as for 'full' /370. The only difference, beside the need to be assembled to tape, was a different subroutine branch instruction (handled by macro anyway) .
    – Raffzahn
    Oct 22 at 13:52

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