Memory sharing mechanism in the Amstrad CPC computer

Question

In the Amstrad CPC464 (and I guess it's the same for CPC664 and 6128), the CRTC and the gate array work together to build the display image: every microsecond, the CRTC puts a memory address and a byte is read, and the gate array receives that byte and converts it to pixels.

The following picture displays the CRTC -> memory interface. A 4:1 mux chooses what address bits are seen by the DRAM memory at different times (RAS address from CRTC, CAS address from CRTC, RAS address from CPU, or CAS address from CPU). The control inputs for this mux are CPU ADDR and CAS ADDR. Note that one of the inputs to the mux is CCLK, which is supposed to be a 1 MHz signal, that clocks the whole CRTC chip.

On the other hand, the gate array stops the CPU using the READY signal. Its data bus is isolated from the memory data bus by using IC114 (controls data flow from CPU to memory) and IC115 (ditto from memory to CPU)

This is all I can infer from the CPC schematics, but I have some doubts about how does it all cooperate:

• The CCLK signal is surnamed MA0 (CCLK/MA0) and goes to the mux, as if it were another address, while MA0 from the CRTC also goes to the mux. Which is the purpose of putting CCLK as a bit address here? NOTE: as I write this question, I'm starting to suspect that the memory access rate could be 1 read every 500 ns, instead of 1 read every 1000 ns, so the gate array have 2 bytes (16 bits) every microsecond, and it is capable of building up to 16 pixels in that time. Am I on the right path about this?

• The CPU ADDR signal is also used (although not shown in these figures) as the AY-3-8910 clock signal, labelled "1 MHz". Is it really a 1 MHz signal. Why didn't they use CCLK instead, which is also a 1 MHz signal? Or put in in other words: why are there two 1 MHz signals?

• How CPU ADDR, CAS ADDR 244EN and READY evolve in time?

Answer 1

My best mental reverse engineering of the constraints applied to the CPC bus, based on reading alone, is that it has a period of four cycles. Disclaimer: I'm not much of an electronics person, just an avid schematic reader as an offshoot of emulator authorship.

The Z80's WAIT, which is the recipient of the gate array's READY is signalled for three out of the four cycles. For argument's sake, say cycles 2–4. Because the Z80 sometimes samples wait during the cycle it intends to access the bus (on opcode reads) but at other times samples it the cycle before it intends to access the bus (on ordinary reads and writes), that pattern boxes the CPU in to accessing on cycles 1 and 2, and leads to the round-up-to-four rule for Z80 machine cycle timing.

The CRTC is clocked at 1Mhz but video memory is read at 2Mhz — e.g. in mode 2 you've got 80 columns of 1bpp text. So that's 80 bytes. It's 40/64ths of the width of the display. So if the CRTC were configured without any syncs, etc, that'd be 128 bytes read per line. Multiply that by the PAL line frequency of 15625Hz and that's exactly 2Mhz (though by not being interlaced usually, the CPC supplies only 624 of the usual 625 lines for each two fields, so actually produces output video at just a tiny bit above 50Hz).

Video bytes are read during cycles 2 and 3. But the CRTC is clocked only once. So a separate clock — CCLK is substituted for the low two bits. The CRTC actually supplies a total of 18 address lines: four for character row plus 14 for character index. The CPC discards the topmost from character row. It keeps the most significant two from the character index but throws replaces the two underneath that with the three it keeps from the character row. So it keeps fifteen of eighteen, and substitutes in CCLK to make the sixteenth.

What that means is that CCLK needs to tick over from 0 to 1 during the transition from cycle 3 to cycle 4. But CPU is used as the input to the multiplexers and the mutiplexers need to change between offering RAM to the CPU and offering it to the gate array during the transition from cycle 2 to cycle 3. So I think they are both 1Mhz clocks, but they're 1/4 of a cycle out of phase. It was then probably arbitrary which one got extended to the AY, which is clocked at 1Mhz. Having checked the data sheet, it doesn't clock anything except audio on its input — bus loading and sampling depends on BC1, BC2 and BDIR as controlled by the 8255 PPI, not on the clock input.

Given that two video bytes are fetched during two consecutive cycles but should be output over the course of four, that implies a cycle where the first byte fetched is still being serialised but the second needs to be put somewhere safe. That's what I think the 74LS244 data buffer most likely does. So 244EN controls the timing of that chip's capture and release.

CASADDR just appears to be the RAS/CAS selector — via each multiplexer it allows the high eight bits of the input address to be RAS and the low to be CAS, or possibly vice versa. Since both the row and column need to be selected every cycle, it likely runs along at 8Mhz.

So, on my account of the four cycle bus: * CPU ADDR is high, high, low, low; * CCLK is high, low, low, high; * READY is high, low, low, low; * CASADDR strobes high and low during every bus cycle; * 244EN acts to instruct the 74LS244 to latch what's on the bus during cycle four, and forward it during the next cycle one.