In the Amstrad CPC464 (and I guess it's the same for CPC664 and 6128), the CRTC and the gate array work together to build the display image: every microsecond, the CRTC puts a memory address and a byte is read, and the gate array receives that byte and converts it to pixels.
The following picture displays the CRTC -> memory interface. A 4:1 mux chooses what address bits are seen by the DRAM memory at different times (RAS address from CRTC, CAS address from CRTC, RAS address from CPU, or CAS address from CPU). The control inputs for this mux are
CPU ADDR and
CAS ADDR. Note that one of the inputs to the mux is
CCLK, which is supposed to be a 1 MHz signal, that clocks the whole CRTC chip.
On the other hand, the gate array stops the CPU using the
READY signal. Its data bus is isolated from the memory data bus by using IC114 (controls data flow from CPU to memory) and IC115 (ditto from memory to CPU)
This is all I can infer from the CPC schematics, but I have some doubts about how does it all cooperate:
CCLKsignal is surnamed
CCLK/MA0) and goes to the mux, as if it were another address, while
MA0from the CRTC also goes to the mux. Which is the purpose of putting
CCLKas a bit address here? NOTE: as I write this question, I'm starting to suspect that the memory access rate could be 1 read every 500 ns, instead of 1 read every 1000 ns, so the gate array have 2 bytes (16 bits) every microsecond, and it is capable of building up to 16 pixels in that time. Am I on the right path about this?
CPU ADDRsignal is also used (although not shown in these figures) as the AY-3-8910 clock signal, labelled "1 MHz". Is it really a 1 MHz signal. Why didn't they use
CCLKinstead, which is also a 1 MHz signal? Or put in in other words: why are there two 1 MHz signals?
READYevolve in time?