But JMP and JSR presumably in general need to jump to anywhere in the program. How do they specify target address? The above document says
Like with any other instruction addressing?
"Bits 5-0 designate the destination field that consists of addressing mode and general register fields. This specifies the starting address of the subroutine."
Keyword here is 'addressing mode'.
Does that mean you have to load the target address into a register in a separate instruction first?
That's one way. Or any other will do.
Addresses in PDP-11 instructions are encoded as a 3 bit mode field (5..3) and 3 bit register field (2..0), the later specifying any of the registers to be used.
Mode itself consists of one of 4 addressing modes (5..4), as there are:
- 00 - Register
- 01 - Autoincrement
- 10 - Autodecrement
- 11 - Index
The remaining one bit (3) indicating indirect (deferred in PDP-11ish).
In case of index, it's a two word instruction with the index to be added to the register as second word. Thus any 16 bit offset can be specified relative to any register - resulting in an arbitrary 16 bit address. For code relative addressing the PC (R7), makes a great base, isn't it? The result should be an even address. It might also be noteworthy, that register direct is not possible, as a register can not contain code :) (*1)
The usage of R7/PC as register also results in additional modes:
- Mode 2 (Autoincrement) becomes immediate (Not useful for JMP/JSR) -
- Mode 3 (Autoincrement Indirect) becomes Absolute -
- Mode 6 (Indexed) is the already mentioned Relative -
It must be noted, that these are not really additionally implemented modes, but rather side effects of using PC. They are merely nice fitting names for inflexible humans. That's why the assembler supports them with a dedicated syntax (*2).
- Mode 0 - illegal
- Mode 1, Register Indirect, jumps to wherever the register points -
- Mode 3, Autoincrement Indirect, jumps to address contained in a word addressed by the register and increments the register by two -
JMP @(R1)+ (*3)
- Mode 6, Indexed, jumps to the result of adding a 16 bit word to the register specified -
- Mode 7, Index Indirect, jumps to address contained in a word addressed by adding a 16 bit word to the register specified -
All of this is usually described in Section 3, Adressing Modes of the processor Handbook, or section 5 of the MACRO-11 manual. I guess the site you're citing doesn't explain it in detail as it's so fundamental that they (like man other) assume that one checking up encoding knows about.
*1 - As Wilson mentions, some PDP-11 variants may allow, under special circumstances, code to reside in a register - still, even these CPUs issue an 'Illegal Instruction' trap when a 'normal' program tries to execute a JMP or JSR in with mode 0 (See p.98 of the PDP-11/20 manual).
*2 - Another great example for the difference between Assembler and Machine-Code. Assembler operates on an abstract level.
*3 - Very handy to build some kind of threaded code structure - did anyone say FORTH?