I don't know whether it's still the case, but at least in the early days, it was common for RAM chips to be one bit wide, so e.g. an 8-bit computer would install them in groups of eight. I gather at least for DRAM, having sixteen kilobytes in the form of eight 16384x1 chips makes the refresh circuitry simpler than if it was eight 2048x8 chips.

I notice some chips were four bits wide. https://www.intel-vintage.info/intelmemory.htm lists specific models; there are plenty of chips, both static and dynamic, with a width of four bits, but only a handful eight bits.

This did have consequences; the Acorn Electron tried for 32K total with a minimum chip count to reduce cost, ended up with a 4-bit data bus, which basically halved its speed. Certainly at a time when the majority of computers had an 8-bit data bus, it would seem intuitively more logical for that to be the width.

So why was x4 so much more common than x8?

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    4 bit made sense also becasue there were some CPUs with 4 bit data bus. Sharp used such CPUs in their pocket computers, like PC-1210/PC-1211 and others. – UncleBod Mar 2 '19 at 7:44
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    A few more computers have a bus width a multiple of 4 and of 1, than have a bus width a multiple of 8. – OmarL Mar 2 '19 at 8:27
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    And some early systems had actually 9 bit memory, 8 bit data bus and one parity bit... – UncleBod Mar 2 '19 at 11:19
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    @UncleBod not really. Parity checked memory didn't arrive in microprocessor systems in noteworthy numbers before the IBM PC - and that was way passed the time the decisions asked here have been made – Raffzahn Mar 3 '19 at 2:40
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    Memory was commonly parity in PC systems so you would actually have nine bits per byte (including onboard ram/cache) only non parity was 8 bits. In the cases of parity ram early designs used single bit chips, when the 4 bit chips came onto the market then the module 30pin (SIP or SIMM) would have (2) 4bit chips and a 1 bit chip. This continuted up though the point where the memory was 4MB x 1bit or 4MB x 4bit. A Sun690MP used a maximum module size of 16MB early versions of that were (36) 1M x 4bit chips. That system also had 2 banks of 16 slots for a total of 512 MB of parity RAM. – Rowan Hawkins Jan 11 '20 at 1:03

I don't know whether it's still the case, but at least in the early days, it was common for RAM chips to be one bit wide, so e.g. an 8-bit computer would install them in groups of eight.

Not really. It depends on the way the Family designers envisioned a certain system. And what the use case in terms of memory needed was. Early RAM chips where all static and organized as x1, x4 or x8. Intel's 1 KiBit Ram was available as 256x4 as 2101 or 1024x1 called 2102.

The 2101 was housed in a 22 pin package, while the 2102 only needed 16. Due to the smaller package these chips could be offered for less, and building systems was even cheaper due the lower pin count. On the backside, it takes 8 chips to get a byte. Applications that need only 256 bytes or less are better off to use nibble wide memories, as with the 2102 only two ships where to be soldered. And while each might be a few percent more expensive than its x1 counterpart, cutting the BOM down from 8 to 2 chips was quite a saving.

Motorola went even a step ahead and made its 1 KiBit chip 6810 byte-wide. Thus, embedded systems with a need of 128 bytes or less could be made with just a single 24 pin IC.

MOS went with the 6550 nibble wide - again to enable small systems at low price - the 6500 was meant to be as cheap as possible.

I notice some chips were four bits wide.

For a short time - and on static RAM - they became the majority, as they allowed to cut down on chips needed. Keep in mind, back then designers didn't just fill up the address space and see if it's needed or not. Also, nibble wide chips could be used in 4 bit as well as 12 bit systems. So it might be a sweet spot.

but only a handful eight bits.

Early on yes, but around 1980 8 bit wide static RAM became the standard. See 6116, 6264, 62256, etc. Much like with (EP)ROM static RAM didn't need multiplexing, thus 8 bit wide is the most simple cost effective design - as long as the memory need can be satisfied by one IC.

And before you ask, 4 bit wide DRAM were a special case. They where especially popular with 256 KiBit RAMs. When organized as 64 Ki by 4 two could be used to fill the whole address space of an 8 bit micro. So similar organization, but different reasoning.

  • Ah, yes. Looking at ads in Byte, December 1977, 2102-1 for $1.50, 2101-1 for $3, so the larger package in that case doubles the price, but in an embedded system where you know the wider chip fully satisfies the memory requirements, it would still overall be cheaper. – rwallace Mar 2 '19 at 11:18
  • Though hang on. In that case going from x1 to x2 costs one extra pin for data, but saves one pin for address. So why not x2 as the baseline, if it would cost nothing extra per chip, and save chips in some cases? – rwallace Mar 2 '19 at 11:23
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    Perfect right. Still, it would need 4 chips, so with your above prices (which I remember as being less than double), a nibble wide chip would have still saved by less thru holes to be made. - also, they can be used as single chip in 4 bit systems. – Raffzahn Mar 2 '19 at 18:15
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    @rwallace: Using an x2 layout would only be helpful in cases where one would only need a single bank. If one would need more than a single bank, using the extra pin for addressing would cut the required number of external chip-select decodes in half. Using x4 will pay off if one needs either one or two banks, or if one needs four banks but they're different sizes (e.g. 2x256KiB and 2x64KiB). – supercat Mar 4 '19 at 16:31

In the case of Intel, their initial manufacturing lines were set up for 16 and 18-pin ceramic DIP packages. Thus, their first memory and processor chips were limited to 16 or 18 pin packages:

4004 Microprocessor1103 DRAM

Intel determined the Busicom design was too complex, since serial memories required more components, and would use 40 pins, a packaging standard different from Intel's own 16-pin standard. Intel proposed to develop a new design which could be produced with standard 16-pin DIP packaging, and would have a reduced instruction set.


It took several years before Intel could afford to upgrade their production lines to larger package sizes.

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    I can understand that packages with more pins are more difficult or expensive to make. Does x8 need more pins than x4? Four extra pins for data? – rwallace Mar 2 '19 at 2:27
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    @rwallace: Correct. The data "width" of a memory chip refers to how many data bits can be read or written at one time, which in turn depends on how many package pins are allocated to data lines. Thus, an 8-bit memory needs 4 more pins than a 4-bit memory (and 7 more than a 1-bit memory). – DrSheldon Mar 2 '19 at 2:38
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    At the same time it needs 3 address pins less. – Raffzahn Mar 2 '19 at 7:36
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    @Raffzahn: When not using a multiplexed address bus, an 8-wide chip would need one fewer address pin than 4-wide. – supercat Mar 4 '19 at 16:33

When using a non-multiplexed address bus, an N-by-4 RAM chip will need two fewer address bits than a 4N-by-1 chip, so even though it has three more data bits, the net gain for moving to an N-by-four organization is only one pin. Expanding to an 8-wide arrangement could save one more address pin, but add four more data pins.

When using multiplexed addresses, boosting the number of addresses by a factor of four would only require adding one extra address pin rather than two, but the benefit of cutting the number of chips by a factor of 4 often make it worth adding three extra chips per.

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