The 1970s saw a big transition from CPUs built from thousands of discrete components, to CPUs implemented on a single chip, with the occasional use of bit-slice components along the way.
There were, however, some CPUs implemented in a couple of chips. Setting aside coprocessors for floating-point and memory management, one division that was used was a chip for control logic and a second chip for registers and ALU, for example some implementations of the PDP-11: http://simh.trailing-edge.com/semi/f11.html
On the one hand that sounds like a logical division. On the other hand, I'm curious about how it worked in specific.
Late-70s microprocessors tended to be limited by pin count; it was tricky and expensive to go beyond 40 pins, which would quickly be eaten up by address bus, data bus and miscellaneous.
So: the control chip reads an instruction word, which decodes as an instruction to add the contents of a pair of registers. It needs to communicate this to the data chip. How does it do so? The control chip doesn't seem like it would have a bunch of spare pins for that communication, and for that matter nor does the data chip. How do they get around this?