Questions tagged [cpu]
The cpu tag has no usage guidance.
82
questions
10
votes
2answers
2k views
When was the 6502 second sourced?
According to https://en.wikipedia.org/wiki/Second_source
MOS Technology licensed Rockwell and Synertek to second-source the 6502 microprocessor and its support components.
This makes sense; the 6502 ...
2
votes
1answer
152 views
Why 8086/8088 has OF in a high Flags byte?
In 8086, OF is put not into low Flags byte as other flags but separated in the second (high) byte. This is followed then in all the x86 line.
Beside the possible historical reasons, this looks highly ...
33
votes
4answers
5k views
Why was manual branch suggestion abandoned?
Once pipelined CPUs became common, a common issue arrived as a result of taking the wrong branch of a conditional jump, and thus needing to flush the pipeline. As a result branch prediction mechanisms ...
10
votes
2answers
2k views
How did the CP1600 CPU supposedly make looping faster?
I came across an Intellivision in a box of stuff. When I looked it up on Wikipedia, it said that it uses a CP1600 that is based off a PDP-11. There's a weird entry on the wiki page:
CP1600 did not ...
7
votes
2answers
258 views
What is the relation between external clock and internal states in the 68000?
(I'm assuming a memory cycle of 500 ns, without wait states.)
According to the 68000 bus diagram, there are 4 CPU cycles for a memory cycle, so an external frequency of 8 MHz. However, things are ...
25
votes
4answers
2k views
Do instruction exercisers exist for 8086 and 68K (and other) CPUs?
For some of retroCPUs there exist exhaustive instruction exercisers, i.e. programs that are capable of catching the implementation errors when run on the emulator under development or on the newly ...
19
votes
1answer
2k views
What are the screws for on the UltraSPARC?
I fail to grasp what can be screwed on them, can you explain what are these for?
0
votes
2answers
181 views
Z80 - "LD (nn), dd" command cycle [closed]
For a university assignment, I have to describe and draw the command cycle of the LD (nn), dd command. To be exact, I was given this command:
LD (0x1000), BC
which I interpret as putting the low ...
1
vote
1answer
281 views
8088 CPU A16-A19 address lines go crazy with nop test after 0FFFF address
I'm building a minimal, minimum mode 8088 computer. I started with an 80C88-2 (CMOS, static variant) CPU. My configuration is really simple. One CPU, one 74HCT245 (DTR->DT/R) for the data lines, ...
2
votes
2answers
406 views
How were the popular CPUs of the eighties implemented? [closed]
With the ubiquity of FPGAs, I find it relatively easy to design an eighties-like CPU. But it's maybe too simple now, with so many ways to implement any given CPU unit.
What were the hardware ...
6
votes
1answer
329 views
Z80, do I need a resistor for pins to Vcc?
Building a Z80 computer after completing one with 65c02.
Z80 on my project needs some pins to be tied high (INT, NMI, WAIT, BUSRQ), these are the ones that I don't need for the time being. There are ...
31
votes
7answers
8k views
Does the industry continue to produce outdated architecture CPUs with leading-edge process?
Intel has named the i7-8086K in honor of the 8086 processor, though itself it is a 64-bit processor. And we still see in embedded systems or MIL-SPEC platforms there are old CPUs like the 80386 ...
23
votes
7answers
5k views
What was the last non-monolithic CPU to come to market?
This answer to the question "What was the rationale behind 36 bit computer architectures?" makes the point that early computers were assembled by hand, rather than having central processing ...
0
votes
1answer
298 views
What's the heritage of 80286? [closed]
80186 introduced some instructions for HLL features.
80286 introduced some instructions for protected mode, and provided some multitasking ability with external MMU which was never intended for PCs ...
3
votes
2answers
358 views
Would there be any practical use of two or more VDPs or sound chips in a retro computer build?
Would that allow for better sound samples or double/triple the number of sprites & colours on screen or would that put too much pressure on the CPU or cause bottlenecks, maybe requiring 2 CPUs for ...
0
votes
2answers
227 views
CPU slaves on a PCI card to retrofit single processor to multiple processors. Any ideas how? [closed]
My desktop computer is no longer manufactured and no longer supported since more than 18 years ago. It was a very expensive top of the line business computer back in the day. I like it and wish to ...
7
votes
2answers
771 views
What was the first microprocessor to overlap loads with ALU ops?
Modern out of order CPUs can do all sorts of things in parallel, having not only multiple functional units, but a lot of logic to check at runtime exactly which instructions really depend on others, ...
7
votes
1answer
1k views
Did any CPU ever expose load delays?
There have been CPUs with exposed branch delays, such as early MIPS: What was the first CPU with exposed pipeline?
(Later MIPS kept the delay slots from the early MIPS, though by that time, it wasn't ...
3
votes
0answers
171 views
Scaling compute times to a Pentium III 700 MHz [closed]
According to a competition programming site, where users can submit single source files to be compiled and run, "programs are run on a modern processor but times are scaled to a 700 MHz Pentium ...
5
votes
1answer
312 views
Did any computer actually use the KR580VM1?
The KR580VM1 (or КР580ВМ1) is a CPU from Soviet Ukraine that is not directly equivalent to any Western ones. It's basically an Intel 8080 with another register pair, H1L1, and another address space ...
4
votes
3answers
2k views
8086 duration of program
I have the following assembly code for 8086
MOV AL, [BX]
OUT DX, AL
The bus clock frequency is 1MHz. Access to memory is done without WAIT, and to I/O with one WAIT tick. How I can calculate the ...
3
votes
0answers
199 views
MIPS Encoding of blez/bgtz vs bltz/bgez
In the MIPS architecture, blez/bgtz and bltz/bgez are encoded differently:
blez/bgtz are encoded as: [BLEZ/BGTZ: 6 bits] [RS: 5 bits] [0: 5 bits] [OFFSET: 16 bits]
bltz/bgez are encoded as: [REGIMM: 6 ...
31
votes
4answers
9k views
Intel CPU bug in the '90s
My teacher who teaches "Logic" at the university told us a story about Intel processors, which goes: In the '90s Intel had a bug in the calculation of mathematical functions like sin/cos ...
54
votes
8answers
9k views
Why didn't early single-chip CPUs support multiplication instructions
Early single-chip silicon CPUs like the Zilog Z80 or MOS 6502 did not have a multiply instruction at all. Was this because the technology did not exist at the time to implement it, was it too ...
5
votes
2answers
1k views
How can I connect this 3-pin Slot 1 CPU fan to my system that uses a 2-pin connector?
I'm trying to put a new CPU cooler in my 1999 IBM Aptiva 2163-580 (which has an Intel 440BX chipset, in case that's relevant). The system uses a Slot 1 CPU.
The old cooler had a 2-pin connector, which ...
13
votes
1answer
2k views
Intel processor transistor type evolution
The Intel 4004 used MOS (metal–oxide–semiconductor) transistors.
What has been the transistor types used in Intel processors onwards from the 4004 to 8085 to the x86 family of instruction set ...
-3
votes
2answers
515 views
Should I install Gentoo i586 packages on my PC? [closed]
I've recently commenced revitalizing an HP Pavilion Slim. She's running an Intel Pentium, x86_64. I thought I'd give Gentoo a go because I've found it very appealing and as a Bedrock user I wanted to ...
11
votes
2answers
662 views
Performance of the Rekursiv
I happened to find out about the Rekursiv today. Rekursiv is a processor that attempted to implement OOP concepts directly at the hardware level.
Since it never got fully developed, I wonder what ...
2
votes
4answers
577 views
Which part of a computer does the conversion between binary to hexadecimal? [closed]
I know most computer architecture store data in binary in drives/storage, but i'm unsure where in a computer (x86, etc) does the conversion/interpretation of binary (base2) to hexadecimal (base16) ...
24
votes
3answers
2k views
How was the 80186 incompatible with the IBM PC?
According to https://en.wikipedia.org/wiki/Intel_80186
The 80186 would have been a natural successor to the 8086 in personal computers. However, because its integrated hardware was incompatible with ...
2
votes
1answer
99 views
Max length of traces / wires for MC680x0 relocator
What is the maximum length of a relocator traces or wires that will reliably send signals to Mother Board of a CDTV. I bought TF536, unfortunately due to miscommunication with the seller the card ...
6
votes
1answer
227 views
When was term "word" first used as reference to CPU max register size
I've tried to find information when term 'word' was firstly used. And it seems that even ENIAC used this term.
Is it safe to say that term 'word' was invented with ENIAC?
6
votes
2answers
288 views
Why was the maximum byte size of 8 bits on IBM 7030?
As far as I know, IBM 7030 used term byte. But this byte was just an imaginary term to make easier for our brain to work with bits. So it had nothing in common with a physical realization of the CPU.
...
5
votes
1answer
282 views
Do all Intel Celeron processors support "FCOMIP"? [closed]
I am interested, did all Celeron processors support the FCOMIP instruction? I've made a compiler for my programming language and it uses FCOMIP for every floating-point comparison. I've noticed that ...
9
votes
4answers
1k views
Why did later CPUs use microcode instead of PLA's?
If you look at a die photo of a 6502, about forty percent of the chip is taken up by what's obviously microcode, both by its regular structure and by the obvious need for such from the instruction set,...
29
votes
8answers
10k views
Why did post-8008 CPUs not keep the on-chip stack idea?
Ken Shirriff writes in his blog entry about the 8008:
The 8008's seven registers are in the upper right. In the lower right is the address stack, which consists of eight 14-bit address words. ...
3
votes
2answers
547 views
What’s the last x86 CPU that didn’t place a limit on the size of a single instruction?
Although useless, it’s widely known the first Intel and derivative CPUs like the Z80 didn’t set a limit on the instruction size. This means that it was possible to fill the whole RAM/ROM with a single ...
0
votes
3answers
477 views
How do multi-byte instructions work?
Let's say you have a hypothetical 8-bit processing machine with 256 bytes of memory. You want to load the value stored in memory location $f2 into a register.
However, with a data bus of just 8 bits, ...
20
votes
2answers
7k views
Why did Socket 3 have more pins than needed for the 486?
Intel's Socket 3, used for 486 processors, was a 19×19 pin grid array socket. However, all compatible processors, to my knowledge, used 17×17 PGA packages. What was the point of the extra pins around ...
34
votes
4answers
8k views
How much did IBM save by limiting the PC to 4.77 MHz?
My understanding is the CPU clock speed on the Intel 8088 in the IBM PC was selected as 4.77 MHz to simplify the design of the system. This despite the 8088 coming in two versions - 5 MHz and 8 MHz. ...
16
votes
2answers
1k views
DEC Alpha: why no 8/16-bit load/stores?
The first version of the DEC Alpha had no load/store instructions for 8 or 16-bit values; if you wanted to deal with data of such sizes, you had to do it by shifting and masking values in registers as ...
19
votes
4answers
5k views
Were there any 8-bit CPUs with 24-bit addressing?
Or was that something that didn't appear until later CPUs (around the time of the 286 maybe)?
Also, how would I go about researching this on my own? It's not exactly something I can look up on ...
3
votes
2answers
318 views
What's the Motorola microprocessor with two sets of registers to avoid costly context switch?
I remember reading somewhere (maybe on Hacker News or Lobsters) that Motorola made a microprocessor some decades ago with two sets of registers. This means when handling an interrupt, it does not need ...
5
votes
2answers
428 views
Why were the Cell SPEs unable to operate without instruction from the PPE? [closed]
The Cell, the CPU of the PlayStation 3, contained one conventional core called the PPE, and up to eight specialized vector cores called SPEs.
According to https://en.wikipedia.org/wiki/Cell_(...
12
votes
6answers
5k views
Did any RISC CPU ever take more than one clock cycle per instruction?
Classic RISC CPUs like ARM and MIPS basically offer the trade-off: simple instruction set, but instructions execute in one cycle for good overall performance. (It gets more complicated in later times, ...
9
votes
3answers
2k views
Did multiplexed address/data lines make memory access slower?
Looking at the pinout of e.g. the 8088, it multiplexes the data lines onto eight of the address lines; presumably the designers judged that being able to squeeze the chip into a 40-pin package, would ...
0
votes
2answers
730 views
Get himem.sys working on an AMI 1.06.09 bios (not on VM)
I tried many 98SE boot disks online, they all boot successfully on my mobile workstation from USB (C:\>), but all can't run the Windows 98SE Installer because of XMS Memory, giving an error like:
...
6
votes
2answers
406 views
8 registers in the 9440?
Looking over the 9440 spec sheet, a question arises. The very first line notes that it has eight registers... eight? There's the four AC's, PC, carry bit (all 16-bits for that one!) and... what? On ...
13
votes
5answers
1k views
Has there ever been a instruction set architecture that did not require instruction decoding at all?
I am studying basic principles of instruction set architectures and am considering what it would take to not have any instruction decoding at all. I.e., all the control lines of the computer would be ...
75
votes
9answers
11k views
Why is the processor instruction called "move", not "copy"?
Many processors have an instruction called "move" (sometimes spelled MOV) which copies data from one location (the "source") to another (the "destination") in registers and/or memory. It does not do ...
