Questions tagged [cpu]
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61
questions
4
votes
3answers
2k views
8086 duration of program
I have the following assembly code for 8086
MOV AL, [BX]
OUT DX, AL
The bus clock frequency is 1MHz. Access to memory is done without WAIT, and to I/O with one WAIT tick. How I can calculate the ...
3
votes
0answers
96 views
MIPS Encoding of blez/bgtz vs bltz/bgez
In the MIPS architecture, blez/bgtz and bltz/bgez are encoded differently:
blez/bgtz are encoded as: [BLEZ/BGTZ: 6 bits] [RS: 5 bits] [0: 5 bits] [OFFSET: 16 bits]
bltz/bgez are encoded as: [REGIMM: 6 ...
30
votes
4answers
9k views
Intel CPU bug in the '90s
My teacher who teaches "Logic" at the university told us a story about Intel processors, which goes: In the '90s Intel had a bug in the calculation of mathematical functions like sin/cos ...
53
votes
8answers
9k views
Why didn't early single-chip CPUs support multiplication instructions
Early single-chip silicon CPUs like the Zilog Z80 or MOS 6502 did not have a multiply instruction at all. Was this because the technology did not exist at the time to implement it, was it too ...
5
votes
2answers
803 views
How can I connect this 3-pin Slot 1 CPU fan to my system that uses a 2-pin connector?
I'm trying to put a new CPU cooler in my 1999 IBM Aptiva 2163-580 (which has an Intel 440BX chipset, in case that's relevant). The system uses a Slot 1 CPU.
The old cooler had a 2-pin connector, which ...
-3
votes
2answers
299 views
Old Intel Pentium PC: am I an i586? Does Gentoo provide i586 packages? What else am I compatible with? [closed]
I've recently commenced revitalizing a very old PC. She's running an Intel Pentium, x86_64. I thought I'd give Gentoo a go because I've found it very appealing and as a Bedrock user I wanted to be ...
11
votes
2answers
631 views
Performance of the Rekursiv
I happened to find out about the Rekursiv today. Rekursiv is a processor that attempted to implement OOP concepts directly at the hardware level.
Since it never got fully developed, I wonder what ...
2
votes
4answers
246 views
Which part of a computer does the conversion between binary to hexadecimal? [closed]
I know most computer architecture store data in binary in drives/storage, but i'm unsure where in a computer (x86, etc) does the conversion/interpretation of binary (base2) to hexadecimal (base16) ...
20
votes
3answers
2k views
How was the 80186 incompatible with the IBM PC?
According to https://en.wikipedia.org/wiki/Intel_80186
The 80186 would have been a natural successor to the 8086 in personal computers. However, because its integrated hardware was incompatible with ...
2
votes
1answer
89 views
Max length of traces / wires for MC680x0 relocator
What is the maximum length of a relocator traces or wires that will reliably send signals to Mother Board of a CDTV. I bought TF536, unfortunately due to miscommunication with the seller the card ...
5
votes
1answer
163 views
When was term “word” first used as reference to CPU max register size
I've tried to find information when term 'word' was firstly used. And it seems that even ENIAC used this term.
Is it safe to say that term 'word' was invented with ENIAC?
3
votes
2answers
191 views
Why was the maximum byte size of 8 bits on IBM 7030?
As far as I know, IBM 7030 used term byte. But this byte was just an imaginary term to make easier for our brain to work with bits. So it had nothing in common with a physical realization of the CPU.
...
5
votes
1answer
269 views
Do all Intel Celeron processors support “FCOMIP”? [closed]
I am interested, did all Celeron processors support the FCOMIP instruction? I've made a compiler for my programming language and it uses FCOMIP for every floating-point comparison. I've noticed that ...
8
votes
4answers
544 views
Why did later CPUs use microcode instead of PLA's?
If you look at a die photo of a 6502, about forty percent of the chip is taken up by what's obviously microcode, both by its regular structure and by the obvious need for such from the instruction set,...
25
votes
6answers
9k views
Why did post-8008 CPUs not keep the on-chip stack idea?
Ken Shirriff writes in his blog entry about the 8008:
The 8008's seven registers are in the upper right. In the lower right is the address stack, which consists of eight 14-bit address words. ...
1
vote
2answers
329 views
What’s the last x86 CPU that didn’t place a limit on the size of a single instruction?
Although useless, it’s widely known the first Intel and derivative CPUs like the Z80 didn’t set a limit on the instruction size. This means that it was possible to fill the whole RAM/ROM with a single ...
0
votes
3answers
278 views
How do multi-byte instructions work?
Let's say you have a hypothetical 8-bit processing machine with 256 bytes of memory. You want to load the value stored in memory location $f2 into a register.
However, with a data bus of just 8 bits, ...
20
votes
2answers
6k views
Why did Socket 3 have more pins than needed for the 486?
Intel's Socket 3, used for 486 processors, was a 19×19 pin grid array socket. However, all compatible processors, to my knowledge, used 17×17 PGA packages. What was the point of the extra pins around ...
30
votes
3answers
8k views
How much did IBM save by limiting the PC to 4.77 MHz?
My understanding is the CPU clock speed on the Intel 8088 in the IBM PC was selected as 4.77 MHz to simplify the design of the system. This despite the 8088 coming in two versions - 5 MHz and 8 MHz. ...
14
votes
2answers
1k views
DEC Alpha: why no 8/16-bit load/stores?
The first version of the DEC Alpha had no load/store instructions for 8 or 16-bit values; if you wanted to deal with data of such sizes, you had to do it by shifting and masking values in registers as ...
19
votes
4answers
5k views
Were there any 8-bit CPUs with 24-bit addressing?
Or was that something that didn't appear until later CPUs (around the time of the 286 maybe)?
Also, how would I go about researching this on my own? It's not exactly something I can look up on ...
3
votes
2answers
269 views
What's the Motorola microprocessor with two sets of registers to avoid costly context switch?
I remember reading somewhere (maybe on Hacker News or Lobsters) that Motorola made a microprocessor some decades ago with two sets of registers. This means when handling an interrupt, it does not need ...
5
votes
2answers
410 views
Why were the Cell SPEs unable to operate without instruction from the PPE? [closed]
The Cell, the CPU of the PlayStation 3, contained one conventional core called the PPE, and up to eight specialized vector cores called SPEs.
According to https://en.wikipedia.org/wiki/Cell_(...
11
votes
6answers
4k views
Did any RISC CPU ever take more than one clock cycle per instruction?
Classic RISC CPUs like ARM and MIPS basically offer the trade-off: simple instruction set, but instructions execute in one cycle for good overall performance. (It gets more complicated in later times, ...
9
votes
3answers
2k views
Did multiplexed address/data lines make memory access slower?
Looking at the pinout of e.g. the 8088, it multiplexes the data lines onto eight of the address lines; presumably the designers judged that being able to squeeze the chip into a 40-pin package, would ...
-1
votes
1answer
510 views
Get himem.sys working on a AMI 1.06.09 bios (not on VM)
I tried many 98SE boot disks online, they all boot successfully on my mobile workstation from USB (C:\>), but all can't run the Windows 98SE Installer because of XMS Memory, giving an error like:
...
6
votes
2answers
389 views
8 registers in the 9440?
Looking over the 9440 spec sheet, a question arises. The very first line notes that it has eight registers... eight? There's the four AC's, PC, carry bit (all 16-bits for that one!) and... what? On ...
12
votes
5answers
1k views
Has there ever been a instruction set architecture that did not require instruction decoding at all?
I am studying basic principles of instruction set architectures and am considering what it would take to not have any instruction decoding at all. I.e., all the control lines of the computer would be ...
70
votes
9answers
9k views
Why is the processor instruction called “move”, not “copy”?
Many processors have an instruction called "move" (sometimes spelled MOV) which copies data from one location (the "source") to another (the "destination") in registers and/or memory. It does not do ...
6
votes
1answer
253 views
Did the CPU test on the Apple //e Diagnostics utility do anything?
After reading about the Apple //e diagnostics card, I noticed on the screenshot below that it reports a CPU test and that the microprocessor is OK:
So I'm curious did the PROCESSOR TEST actually do ...
21
votes
1answer
991 views
MOS 8502, just a 6510B?
I'm looking over what little I can find on the 8502, and from what I can see it appears to be a 2 MHz version of the 6510 with an extra I/O pin.
Much ado about the speed, but the Atari's 6502B's were ...
38
votes
1answer
3k views
Z80 CPU address lines not stable
I just got a Z84C0020PEC and wired it up to test it, using this circuit:
Except that I've added LEDs to A0 through A9. It appears that A0 through A6 operate correctly, but A7 though A9 (I've not ...
6
votes
2answers
805 views
GPU chip implementation on CPU - will it be faster? [closed]
So, modern video cards include two devices - a video signal generator and a graphic accelerator.
The first of them converts data from video memory into MDA / CGA / VGA / RCA / DVI / HDMI / etc format....
6
votes
1answer
429 views
Modern Alternative to Malvino's Digital Computer Electronics
For those who want to study retro computing in depth, starting by understanding 74xxx logic and CPU design is (IMHO), one of the best paths there is. Malvino's "Digital Computer Electronics" (DCE), ...
9
votes
6answers
3k views
Is there any music source code for sound chips? [closed]
I’ll clarify what I mean. The sound chip (c64's SID, spectrum's Yamaha, etc.) is connected either to the input / output port, which will be reserved for the sound chip, or directly to the CPU data bus....
6
votes
5answers
513 views
Could the Intel 8086 CPU have many segments in memory of the same type?
The Intel 8086 CPU could address up to 1 MB of memory using segmentation, and this CPU have 4 segment registers, which are CS and SS and DS and ES.
Each segment in memory can have a maximum size of ...
13
votes
5answers
2k views
Does the Intel 8086 CPU have user mode and kernel mode?
Does the Intel 8086 CPU have user mode and kernel mode as modern CPUs do? and if it doesn't have user mode and kernel mode, does that mean that any user program written for the Intel 8086 CPU could do ...
4
votes
3answers
513 views
How does states, bus cycles and clock cycles differ in the M68000?
I'm trying to understand the difference in bus cycles, clock cycles and states within a 68000 processor.
According to the user manual,
A bus cycle consists of eight states...
Lets assume the 68K ...
1
vote
1answer
351 views
Why doesn't the Intel 8086 CPU use real memory addresses? [duplicate]
The address bus of the Intel 8086 CPU is 20-bits, and when you want to specify a memory address to read from or write to, you would form the memory address using a segment register and an offset ...
13
votes
7answers
5k views
Does the Intel 8085 CPU use real memory addresses?
The Intel 8086 CPU uses memory segmentation, which means that when, for example, you write the value 123 to the memory address 1001, the memory address 1001 will actually get converted first into ...
6
votes
1answer
353 views
Tannenbaum paper on constants in ISAs?
I see many references to a paper by Andrew Tanenbaum that demonstrated the vast majority of constants would fit into 13-bits, and I seem to recall it being in my university text on CPU design. However,...
27
votes
3answers
6k views
Why did Intel abandon unified CPU cache?
When Intel introduced the 80486 in 1989, they included their first on-chip cache, ostensibly to compete better with Motorola, who had been including on-chip caches for 5 years (MC68020, 1984).
Unlike ...
3
votes
2answers
676 views
How exactly do all control signals in 6502 work?
I'm trying to make a 6502 replica in Logisim. I want to know what exactly each control signal in 6502, how the clock cycles work and additionally I would like to see an example of these control ...
11
votes
1answer
774 views
How did the Zip Chip and RocketChip accelerators work for the Apple II?
Though there is already a similar question on the site, this one is more specific to these chips and their technical implementation.
There were two accelerators for the Apple II series that were drop-...
20
votes
7answers
17k views
What does the “x” in “x86” represent?
I have read the following in the x86 Wikipedia page:
The term "x86" came into being because the names of several successors to Intel's 8086 processor end in "86", including the 80186, 80286, 80386 ...
22
votes
2answers
5k views
What was the last x86 CPU that did not have the x87 floating-point unit built in?
This Wikipedia page says the following:
Most x86 processors since the Intel 80486 have had these x87
instructions implemented in the main CPU
So the above quote implies that some CPUs that were ...
13
votes
4answers
1k views
How did 2-chip CPUs work?
The 1970s saw a big transition from CPUs built from thousands of discrete components, to CPUs implemented on a single chip, with the occasional use of bit-slice components along the way.
There were, ...
33
votes
2answers
4k views
Can an x86 CPU running in real mode be considered to be basically an 8086 CPU?
When an x86 CPU is running in real mode, can it be considered to be basically an 8086 CPU (or maybe 8088)? Or are there differences between the two?
31
votes
2answers
6k views
How did people program for Consoles with multiple CPUs?
I'm specifically interested in the Sega Mega Drive/Genesis, which used a 68000 CPU, but also a Z80, mainly used to control the sound hardware and provide backward compatibility with the Master System.
...
4
votes
1answer
421 views
Did the 286 go out of its way to follow the 8088 bus protocol?
In general, different CPUs don't use the same bus protocol. A 16-bit CPU would not in general be expected to use the same protocol as an 8-bit CPU. For example, the 68000 would not be expected to use ...
