Questions tagged [instruction-set]
For questions regarding the instruction sets of microprocessors.
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Is there a comprehensive description of the Electrologica X1/X8 instruction set?
The Electrologica X1, and its successor X8 were word-based computers with 27-bit words, using 1's complement binary arithmetic. In an article comparing Algol-60 compilers for X1 and X8 F. E. J. ...
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Why does the 68000 have Immediate addressing modes for byte-width instructions?
Motorola's 68000 has an instruction like ori.b #immediate, d0. This particular instruction is encoded as all zeroes, followed by a full 16 bits encoding an 8-bit immediate value. The instruction word ...
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What was the 6-bit length instruction(s) in the Intel iAPX 432?
The iAPX 432 was arguably the most complex processor architecture ever and a commercial failure for Intel. It was a stack machine with no visible general-purpose registers. It had hardware support ...
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Did any processor implement an integer square root instruction?
Has any processor ever implemented an integer square root instruction? Obviously, floating-point square root instructions are quite common, but I've never seen one specifically for integers.
One close ...
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What aspects of microprocessor ISAs have been patented?
A key objective of RISC-V was that every aspect of the ISA must be based on an expired patent. It was felt that this is the only truly reliable defense against patent lawsuits.
It is surprising that ...
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Why does the Z22 have a read-only shadow of the return address location?
For some context to this question see Raffzahn's excellent question and answer How were Zuse Z22 Instructions Encoded?.
The Z22 treats the first few locations of its address space in a particular way:...
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Original instruction set for the first ARM processor
I'm studying ISAs and would really like to see the very first ISA that Sophie Wilson chose/put together when designing the very first ARM CPU while at Acorn Computers around 1983 or so.
From what I ...
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IMPI Instruction set: is there any reference?
I've had an IBM 9404 B-10 for some time and I'm curious about its assembly language. I'm fully aware the AS lines were designed with portability in mind as much IBM didn't seem to provide assembly ...
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Would compare-and-branch have added an extra cycle on ARM-1?
The ARM-1 was an early RISC CPU, designed in 1986 (and even more typical of early RISC design constraints than the year would suggest, since Acorn didn't have the budget to pay for the latest process ...
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Why does the LGP-30 leave half its instruction word unused?
I am looking at the machine code for the LGP-30, which is found to have a very strange instruction word layout.
12 ignored bits
4 bits for the opcode
2 more ignored bits
12 bits for the operand, ...
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Is there a CPU ISA preferring a test for the value of one over testing for zero?
While discussing a question about the origin of Zero as value for the default exit code for success, I reflected if there is any Instruction Set Architecture or implementation thereof where testing a ...
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Carry handling during address generation on a 6502
I'm trying to learn a bit more about the internal workings of the 6502.
The manual says that the branch instructions do not affect the carry flag. However, my understanding is that some carry handling ...
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Null-terminated strings on the PDP-7?
I came across a post that states that Unix uses null-terminated strings, ASCIZ, because it was a feature of the PDP-7. This triggered my reading on the CIS instructions in the PDP-11, but these were ...
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What are the “building bricks” of ARM’s design that this magazine article is referring to?
I came across an early mention of the ARM in New Scientist of June 18, 1987:
https://books.google.ca/books?id=LvhAoKR-ixwC&pg=PA41
It has this statement:
They realised that many of the ...
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What motivated the weird boolean instruction repertoire of the PDP-11?
The PDP-11 has seven dyadic instructions (I'm not counting the byte/word varieties separately), which take a full six bits for each of its operands. That's twelve bits to specify the operands, and ...
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Why does the x86 not have an instruction to obtain its instruction pointer?
This has always confused me. Why can you not directly obtain the IP, and instead have to go through some odd assembly hoops such as calling a function whose only purpose is to push its own return ...
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What was the first CPU/FPU without a hardware square-rooter?
The first programmable, electronic, general-purpose digital computer, ENIAC had a "square rooter":
five of the accumulators were controlled by a special divider/square-rooter unit to ...
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Have there been any instruction sets with an odd register width?
Did any early instruction sets have an odd integer register width? The reason I am asking is because all of the instruction sets I have read about (on this site and elsewhere) have had an even general ...
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Was leaving all xxxxxx11 opcodes unused on the 6502 a deliberate design choice?
The 6502, like many 8-bit processors, has a somewhat arcane opcode-mode restrictions. On most such processors, the restriction is a clear result of trying to pack a lot of instructions into a limited ...
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How did the Motorola MC68030 and MC68040 come to have the powerful and expensive CAS2 instruction?
The CAS2 instruction - double compare-and-swap - is an extremely powerful instruction that was coveted for quite awhile (and still is, really) for making lock-free and wait-free data structures - that ...
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Why did instruction sets since the late 1970s seemingly stop including an "execute" instruction?
Many mainframe instruction set architectures (ISAs) in the 1960s included an Execute instruction, which would treat data as an instruction.
I haven't found an architecture designed after 1976 which ...
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Did any core-memory computers have a read-and-erase instruction?
Magnetic core, the primary form of computer memory from the mid-fifties to the early seventies or thereabouts, had the slightly awkward property that reading it erased it, so every time the CPU ...
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Origin of "arithmetic" and "logical" for signed and unsigned shifts
The assembly language for many processors use the phrase "arithmetic shift" to represent the bitwise shift of a signed value, and "logical shift" for an unsigned value. The two ...
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When did the IBM 650 have a "Table lookup on Equal" instruction?
In 1959, Donald Knuth wrote an assembly program named SuperSoap for the IBM 650. Here is the manual, and here is a listing of the program (in SuperSoap assembly language). Quoting from the abstract:
...
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Ratio of code density between 8080 and Z80
The Z80 was (except for a handful of tiny incompatibilities) a superset of the 8080, adding a number of new instructions as well as the alternate register set. It seems therefore that it must have at ...
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Are the 6809 and 6809E different from a programmer's point of view?
I can see the pinouts of these two chips are utterly different. Apparently the 'E needs an external clock as well. This question isn't so much about any of those hardware related differences. This ...
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Why does the Z80 not have EX DE, IX?
Reading Decoding Z80 Opcodes, There's a section about the 0xDD prefix. This instruction prefix causes the next instruction to use the IX register instead of the HL register. That makes sense. HL and ...
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What is the purpose of the "difference of absolute values" instruction?
The IBM NORC computer, among others, had an arithmetic instruction computing the difference of the absolute values of its operands (|x|-|y|, see NORC Programming Manual, page 11, opcode 28), which ...
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Did any 16-bit or 36-bit computer instruction set ever include 4x4 or 6x6 bit-matrix operations?
Donald Knuth's 64-bit MMIX architecture includes several novel instructions that operate matrixwise on an 8x8 square matrix (MOR, MXOR).
(MMIX also has instructions like BDIF that operate vectorwise ...
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Are there any CHIP-8 games that break if `SAVE` / `RESTORE` *doesn't* change the pointer register?
The CHIP-8 instructions SAVE Vx (Fx55) and RESTORE Vx (Fx65) are originally specified to increment the pointer register I as each register is saved/loaded, so by the end of the instruction, the value ...
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Is scratchpad register 15 directly addressable on the F3850 (except as QL)?
The Fairchild F8 CPU, the F3850, has 64 scratchpad registers.
The first 12 of these are directly addressable by several instructions. For example, the opcodes $CX add the contents of scratchpad ...
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What are the added opcodes for MC6801/MC6803?
What new opcodes were added to Motorola MC6801/MC6803?
Background for the question, and what I've figured out so far (correct me if I'm wrong):
The Motorola MC6801 (and MC6803) had an "enhanced ...
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What’s the last x86 CPU that didn’t place a limit on the size of a single instruction?
Although useless, it’s widely known the first Intel and derivative CPUs like the Z80 didn’t set a limit on the instruction size. This means that it was possible to fill the whole RAM/ROM with a single ...
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How do multi-byte instructions work?
Let's say you have a hypothetical 8-bit processing machine with 256 bytes of memory. You want to load the value stored in memory location $f2 into a register.
However, with a data bus of just 8 bits, ...
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6502 - AND instruction updates flags differently than other logic operations
Why AND instruction updates flags in the fetch step?
Others logic instructions like ORA and EOR update flags in the same step that they update accumulator, in the decode step.
Is it a bug of ...
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What are the "ports" used via IN/OUT, vs. the PEEK/POKE address space?
This is something of a followup to How much control of TRS-80 Model III disk drives was possible from its Cassette (ROM) BASIC? but on a more general topic:
I know that PEEK and POKE enable direct ...
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How did the 6502 ALU perform a decrement?
Assuming that this diagram is correct:
Instructions like INC, INX, and INY can easily perform increment using ALU sum with data on B input, 0 on A input and carry_in set.
But how do instructions like ...
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Reconstruct the loop from "The Story of Mel"
From Ed Nather's hacker-epic "The Story of Mel" (using the original paragraph-formatting to save space in this question):
The firm manufactured the LGP-30, a small, cheap (by the standards ...
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Has there ever been a instruction set architecture that did not require instruction decoding at all?
I am studying basic principles of instruction set architectures and am considering what it would take to not have any instruction decoding at all. I.e., all the control lines of the computer would be ...
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Why is the processor instruction called "move", not "copy"?
Many processors have an instruction called "move" (sometimes spelled MOV) which copies data from one location (the "source") to another (the "destination") in registers and/or memory. It does not do ...
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Why are branches relative in many 8-bit CPUs?
I was looking over an old article on the 6809 and was perusing the opcodes and noticed that the branch instructions came in two flavors, long and short. That sparked a memory about one of the 6502-...
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What happened to the SEV instruction on the 6502?
The 6502 has a group of opcodes which copy bit 5 from the opcode into one of the status flags.
(I know it's not implemented this way, but it looks as though the bit fields are: 2 bits to select the ...
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In what way does the Straight-8 expand on the PDP-5?
A quote from the Wikipedia:
The PDP-5's instruction set was later expanded in its successor, the PDP-8, to handle more bit rotations and to increase the maximum memory size from 4K words to 32K ...
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SYNC and the 65CE02 instruction timing
From the Wikipedia's 65CE02 page:
Internally, the pipeline of the 65CE02 was redesigned to reduce the
number of cycles required to execute an instruction. The 65CE02 can
recover faster from ...
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Behavior of the zero and negative/sign flags on classic instruction sets
It seems to me that there's effectively two ways that the zero bit could work.
Z is set iff the result of a computation is mathematically equal to 0.
Z is set iff a bit pattern consisting entirely of ...
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What did the 8086 (and 8088) do upon encountering an illegal instruction?
Preface: This question does in part intersect with Use of undocumented opcodes, but targets especially the 8086 instruction handling.
I was reading Tanenbaum's "Operating Systems, Design and ...
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Why does the 6502 have the BIT instruction?
The 6502 has a bit instruction which
copies two of the bits into the N and V flags,
pretends to and the byte with the accumulator, but discards the result and only affects Z.
I'm having a hard time ...
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How were Zuse Z22 Instructions Encoded?
The title says it all:
How to En-/Decode Z22/Z23 Instructions?
(History and Linkage:
The question was raised by Wilson in a comment on my answer to his question "Why are PDP-7-style microprogrammed ...
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Why are PDP-7-style microprogrammed instructions out of vogue?
DEC, and at least some of their computers, especially those in the 18-bit family and 12-bit family, had these opr instructions, which contained many bitfields which encoded something like "...
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How did the 8086 interface with the 8087 FPU coprocessor?
The 8087 has many instructions - too many, it seems, to be encoded as part of the 8086 instruction set. How did the Intel 8086 interface with an Intel 8087 FPU that a user added?
Consider the ...
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