Questions tagged [instruction-set]

For questions regarding the instruction sets of microprocessors.

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16
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3answers
2k views

Are the 6809 and 6809E different from a programmer's point of view?

I can see the pinouts of these two chips are utterly different. Apparently the 'E needs an external clock as well. This question isn't so much about any of those hardware related differences. This ...
5
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1answer
570 views

Why does the Z80 not have EX DE, IX?

Reading Decoding Z80 Opcodes, There's a section about the 0xDD prefix. This instruction prefix causes the next instruction to use the IX register instead of the HL register. That makes sense. HL and ...
8
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1answer
284 views

What is the purpose of the “difference of absolute values” instruction?

The IBM NORC computer, among others, had an arithmetic instruction computing the difference of the absolute values of its operands (|x|-|y|, see NORC Programming Manual, page 11, opcode 28), which ...
9
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2answers
1k views

Did any 16-bit or 36-bit computer instruction set ever include 4x4 or 6x6 bit-matrix operations?

Donald Knuth's 64-bit MMIX architecture includes several novel instructions that operate matrixwise on an 8x8 square matrix (MOR, MXOR). (MMIX also has instructions like BDIF that operate vectorwise ...
4
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1answer
95 views

Are there any CHIP-8 games that break if `SAVE` / `RESTORE` *doesn't* change the pointer register?

The CHIP-8 instructions SAVE Vx (Fx55) and RESTORE Vx (Fx65) are originally specified to increment the pointer register I as each register is saved/loaded, so by the end of the instruction, the value ...
8
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1answer
114 views

Is scratchpad register 15 directly addressable on the F3850 (except as QL)?

The Fairchild F8 CPU, the F3850, has 64 scratchpad registers. The first 12 of these are directly addressable by several instructions. For example, the opcodes $CX add the contents of scratchpad ...
12
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1answer
192 views

What are the added opcodes for MC6801/MC6803?

What new opcodes were added to Motorola MC6801/MC6803? Background for the question, and what I've figured out so far (correct me if I'm wrong): The Motorola MC6801 (and MC6803) had an "enhanced ...
1
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2answers
322 views

What’s the last x86 CPU that didn’t place a limit on the size of a single instruction?

Although useless, it’s widely known the first Intel and derivative CPUs like the Z80 didn’t set a limit on the instruction size. This means that it was possible to fill the whole RAM/ROM with a single ...
0
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3answers
269 views

How do multi-byte instructions work?

Let's say you have a hypothetical 8-bit processing machine with 256 bytes of memory. You want to load the value stored in memory location $f2 into a register. However, with a data bus of just 8 bits, ...
4
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1answer
773 views

6502 - AND instruction updates flags differently than other logic operations

Why AND instruction updates flags in the fetch step? Others logic instructions like ORA and EOR update flags in the same step that they update accumulator, in the decode step. Is it a bug of ...
15
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1answer
1k views

What are the “ports” used via IN/OUT, vs. the PEEK/POKE address space?

This is something of a followup to How much control of TRS-80 Model III disk drives was possible from its Cassette (ROM) BASIC? but on a more general topic: I know that PEEK and POKE enable direct ...
19
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1answer
2k views

How did the 6502 ALU perform a decrement?

Assuming that this diagram is correct: Instructions like INC, INX, and INY can easily perform increment using ALU sum with data on B input, 0 on A input and carry_in set. But how do instructions ...
22
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1answer
581 views

Reconstruct the loop from “The Story of Mel”

From Ed Nather's hacker-epic "The Story of Mel" (using the original paragraph-formatting to save space in this question): The firm manufactured the LGP-30, a small, cheap (by the standards ...
12
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5answers
989 views

Has there ever been a instruction set architecture that did not require instruction decoding at all?

I am studying basic principles of instruction set architectures and am considering what it would take to not have any instruction decoding at all. I.e., all the control lines of the computer would be ...
70
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9answers
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Why is the processor instruction called “move”, not “copy”?

Many processors have an instruction called "move" (sometimes spelled MOV) which copies data from one location (the "source") to another (the "destination") in registers and/or memory. It does not do ...
19
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4answers
3k views

Why are branches relative in many 8-bit CPUs?

I was looking over an old article on the 6809 and was perusing the opcodes and noticed that the branch instructions came in two flavors, long and short. That sparked a memory about one of the 6502-...
41
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3answers
5k views

What happened to the SEV instruction on the 6502?

The 6502 has a group of opcodes which copy bit 5 from the opcode into one of the status flags. (I know it's not implemented this way, but it looks as though the bit fields are: 2 bits to select the ...
5
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3answers
342 views

In what way does the Straight-8 expand on the PDP-5?

A quote from the Wikipedia: The PDP-5's instruction set was later expanded in its successor, the PDP-8, to handle more bit rotations and to increase the maximum memory size from 4K words to 32K ...
9
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1answer
339 views

SYNC and the 65CE02 instruction timing

From the Wikipedia's 65CE02 page: Internally, the pipeline of the 65CE02 was redesigned to reduce the number of cycles required to execute an instruction. The 65CE02 can recover faster from ...
10
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3answers
1k views

Behavior of the zero and negative/sign flags on classic instruction sets

It seems to me that there's effectively two ways that the zero bit could work. Z is set iff the result of a computation is mathematically equal to 0. Z is set iff a bit pattern consisting entirely of ...
47
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4answers
10k views

What did the 8086 (and 8088) do upon encountering an illegal instruction?

Preface: This question does in part intersect with Use of undocumented opcodes, but targets especially the 8086 instruction handling. I was reading Tanenbaum's "Operating Systems, Design and ...
33
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5answers
6k views

Why does the 6502 have the BIT instruction?

The 6502 has a bit instruction which copies two of the bits into the N and V flags, pretends to and the byte with the accumulator, but discards the result and only affects Z. I'm having a hard time ...
13
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1answer
453 views

How were Zuse Z22 Instructions Encoded?

The title says it all: How to En-/Decode Z22/Z23 Instructions? (History and Linkage: The question was raised by Wilson in a comment on my answer to his question "Why are PDP-7-style microprogrammed ...
16
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4answers
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Why are PDP-7-style microprogrammed instructions out of vogue?

DEC, and at least some of their computers, especially those in the 18-bit family and 12-bit family, had these opr instructions, which contained many bitfields which encoded something like "...
37
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1answer
4k views

How did the 8086 interface with the 8087 FPU coprocessor?

The 8087 has many instructions - too many, it seems, to be encoded as part of the 8086 instruction set. How did the Intel 8086 interface with an Intel 8087 FPU that a user added? Consider the ...
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3answers
1k views

Was there a Western computer with blatantly missing instructions in the instruction set?

In the BESM-6, there is an instruction (045) to add index registers, but not to subtract them, however, there is a nearby unused opcode 047, which is made synonymous to 045 (in fairness, that's true ...
9
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5answers
4k views

What was the main purpose of bitshift instructions in CPU?

As far as I know, even simple RISC microcontroller have a bitshift operator, and honestly I had to use it only once when I had to compute a division on a MCU that could not do divisions in the ALU. ...
-4
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4answers
508 views

Operating systems which have non-x86 instruction set architecture [closed]

What are the most famous operating systems for non-x86 computers? I mean, most famous OS which have different instruction set architecture. Background (to better understand my task): I ask this ...
8
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1answer
517 views

How can floating point addition be so slow on a BESM-6?

In the BESM-6 technical manuals — for example, in the ALU description, page 4 — there is a table specifying min/max/average instruction latencies in clock cycles (the last 3 columns; the ...
27
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3answers
4k views

Why does an instruction include the address of the next instruction on the IBM 650?

The IBM 650 seems to be a load-store machine. One advantage of a load-store machine is that the instruction can be shorter because there's less pressure to pack more information into it. But the IBM ...
7
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4answers
647 views

Which CPUs had instructions leaving data registers in an unspecified state?

When an ALU performs a floating point division operation using the non-restoring or the SRT algorithm, it maintains the current value of the "remainder" (in quotes, because it is not a true non-...
17
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1answer
2k views

Which undocumented 8085 instructions is Steven Morse referring to in “In The Beginning”?

In S. P. Morse's 1980 allegory, "In The Beginning", he writes And Intel said, "Let there be an 8085 with an oscillator on the same chip as the processor, and let an on-chip system controller ...
11
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3answers
1k views

What is the instruction set of the Z4?

I am able to find a few instructions, such as: Fin (presumably "Fine", as in the end of a musical score, ends a program), Fin', (a conditional Fin), St (possibly "Start" -- the need for this is ...
8
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2answers
696 views

Instruction set support for multiplication with a constant

Before integer multipliers in silicon, several cpus had some support for multiplication. For instance SPARCv7 has the MULScc multiply-step instruction (several other cpus also have this). As far as ...
11
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3answers
769 views

How to keep the instruction prefetcher filled up

My understanding is that the Intel 8088 has this buffer which reads ahead in the instruction stream whenever it has a spare bus cycle or two, so that when the time comes to execute that instruction, ...
6
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2answers
1k views

What is the purpose of the ω register of the БЭСМ-6?

This page describing the БЭСМ-6 instruction set refers to a value called ω, which is stored inside a Mode Register. It appears to be set by certain kinds of instructions, so that ω can tell you which ...
10
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2answers
973 views

What is the history of the PDP-11 MARK instruction?

The PDP-11 MARK instruction was intended to be used as part of the standard PDP-11 subroutine return convention. MARK facilitated the stack clean up procedures involved in subroutine exit. To use it, ...
15
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8answers
5k views

Uses for the halt instruction?

What was the halt instruction in early CPUs such as the Z80 and 8080 used for? Here's a description of the Z80 instruction: The HALT instruction suspends CPU operation until a interrupt or reset ...
21
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4answers
3k views

Why does the Z80 include the RLD and RRD instructions?

The Z80 has an instruction RLD, which apparently treats the lower 4 bits in the accumulator and the full 8 bits in (HL) as a twelve bit integer which it then rotates left by 4 bits. The carry flag ...
10
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3answers
1k views

Intel 8080 - Behaviour of the carry bit when comparing a value with 0

I'm in the process of writing an emulator for the Intel 8080. The description of the CMP instruction from Intel's 8080 programming manual (see page 20) says the following: The specified byte is ...
12
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1answer
2k views

Nintendo 64 microcode format

The Nintendo 64 GPU ('Reality Coprocessor') had microcode that could be loaded at runtime. Several standard microcodes were supplied with the development kit, and the easily findable documentation ...
34
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3answers
4k views

Why are first four x86 GPRs named in such unintuitive order?

On x86 the first four general-purpose registers are named AX, CX, DX, BX. It would be quite intuitive if their indices (those used in instruction encoding) were in alphabetical order, but instead of ...
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4answers
1k views

Are there any articles elucidating the history of the POPCOUNT instruction?

Figuring out how many bits in a group of bits are set to 1, known as computing "population count", Hamming weight, or "bit summation", among others, has various applications. It is also fairly cheap ...
42
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8answers
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Executable ASCII files before x86?

I've known about a technique allowing to bootstrap arbitrary 16-bit x86 code from a subset of instructions representable as printable ASCII bytes since the early 1990s. The first example of an ASCII ...
20
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3answers
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PDP-11 instruction set inconsistencies

The wiki page PDP-11 architecture has a cryptic paragraph with no references or examples: Inconsistent instructions Over the life of the PDP-11, subtle differences arose in the implementation of ...
28
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1answer
3k views

What is the relative code density of 8-bit microprocessors?

When RAM is at a premium, as it was in the old days, a greater code density of an instruction set can be a substantial advantage. (Click saver: Code density refers loosely to how many microprocessor ...
3
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0answers
690 views

What are some programs known to take advantage of Intel MMX instructions? [closed]

Although MMX techology, introduced in 1997, is long superseded by SSE series of extensions, it's still included in every modern x86 CPU for backwards compatibility. What are some examples of ...
8
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1answer
401 views

Was there ever a division instruction with sign of the remainder following the sign of the quotient?

A document about the precursor to ANDF (Architecture Neutral Distribution Format) mentions that two of its integer division/remainder primitives "are those generally implemented directly by processor ...
9
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1answer
451 views

Timing and microcode in the PDP-11/40

I've been trying to figure out how the sequence of microcode instructions as described in the schematics and ROM listing in the PDP-11/40 (KD11-A Processor) relates to the timings given in Appendix C ...
10
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3answers
852 views

Was the PDP-11 coroutine instruction actually used?

In a typical description of the coroutine mechanism it usually mentioned that the PDP-11 instruction set provided a way to effect the coroutine switch by a single instruction, namely JSR PC,@(SP)+. ...