Questions tagged [instruction-set]

For questions regarding the instruction sets of microprocessors.

Filter by
Sorted by
Tagged with
6 votes
5 answers
482 views

Is there a CPU ISA preferring a test for the value of one over testing for zero?

While discussing a question about the origin of Zero as value for the default exit code for success, I reflected if there is any Instruction Set Architecture or implementation thereof where testing a ...
  • 183k
12 votes
1 answer
882 views

Carry handling during address generation on a 6502

I'm trying to learn a bit more about the internal workings of the 6502. The manual says that the branch instructions do not affect the carry flag. However, my understanding is that some carry handling ...
13 votes
2 answers
1k views

Null-terminated strings on the PDP-7?

I came across a post that states that Unix uses null-terminated strings, ASCIZ, because it was a feature of the PDP-7. This triggered my reading on the CIS instructions in the PDP-11, but these were ...
10 votes
1 answer
1k views

What are the “building bricks” of ARM’s design that this magazine article is referring to?

I came across an early mention of the ARM in New Scientist of June 18, 1987: https://books.google.ca/books?id=LvhAoKR-ixwC&pg=PA41 It has this statement: They realised that many of the ...
31 votes
4 answers
3k views

What motivated the weird boolean instruction repertoire of the PDP-11?

The PDP-11 has seven dyadic instructions (I'm not counting the byte/word varieties separately), which take a full six bits for each of its operands. That's twelve bits to specify the operands, and ...
  • 35.7k
18 votes
7 answers
5k views

Why does the x86 not have an instruction to obtain its instruction pointer?

This has always confused me. Why can you not directly obtain the IP, and instead have to go through some odd assembly hoops such as calling a function whose only purpose is to push its own return ...
4 votes
2 answers
1k views

What was the first CPU/FPU without a hardware square-rooter?

The first programmable, electronic, general-purpose digital computer, ENIAC had a "square rooter": five of the accumulators were controlled by a special divider/square-rooter unit to ...
  • 16.8k
19 votes
7 answers
4k views

Have there been any instruction sets with an odd register width?

Did any early instruction sets have an odd integer register width? The reason I am asking is because all of the instruction sets I have read about (on this site and elsewhere) have had an even general ...
  • 297
24 votes
2 answers
3k views

Was leaving all xxxxxx11 opcodes unused on the 6502 a deliberate design choice?

The 6502, like many 8-bit processors, has a somewhat arcane opcode-mode restrictions. On most such processors, the restriction is a clear result of trying to pack a lot of instructions into a limited ...
  • 30.9k
19 votes
1 answer
2k views

How did the Motorola MC68030 and MC68040 come to have the powerful and expensive CAS2 instruction?

The CAS2 instruction - double compare-and-swap - is an extremely powerful instruction that was coveted for quite awhile (and still is, really) for making lock-free and wait-free data structures - that ...
  • 4,767
16 votes
3 answers
909 views

Why did instruction sets since the late 1970s seemingly stop including an "execute" instruction?

Many mainframe instruction set architectures (ISAs) in the 1960s included an Execute instruction, which would treat data as an instruction. I haven't found an architecture designed after 1976 which ...
11 votes
2 answers
412 views

Did any core-memory computers have a read-and-erase instruction?

Magnetic core, the primary form of computer memory from the mid-fifties to the early seventies or thereabouts, had the slightly awkward property that reading it erased it, so every time the CPU ...
  • 50.7k
14 votes
2 answers
1k views

Origin of "arithmetic" and "logical" for signed and unsigned shifts

The assembly language for many processors use the phrase "arithmetic shift" to represent the bitwise shift of a signed value, and "logical shift" for an unsigned value. The two ...
  • 14.4k
22 votes
1 answer
1k views

When did the IBM 650 have a "Table lookup on Equal" instruction?

In 1959, Donald Knuth wrote an assembly program named SuperSoap for the IBM 650. Here is the manual, and here is a listing of the program (in SuperSoap assembly language). Quoting from the abstract: ...
  • 3,377
12 votes
1 answer
470 views

Ratio of code density between 8080 and Z80

The Z80 was (except for a handful of tiny incompatibilities) a superset of the 8080, adding a number of new instructions as well as the alternate register set. It seems therefore that it must have at ...
  • 50.7k
18 votes
3 answers
3k views

Are the 6809 and 6809E different from a programmer's point of view?

I can see the pinouts of these two chips are utterly different. Apparently the 'E needs an external clock as well. This question isn't so much about any of those hardware related differences. This ...
  • 35.7k
16 votes
1 answer
1k views

Why does the Z80 not have EX DE, IX?

Reading Decoding Z80 Opcodes, There's a section about the 0xDD prefix. This instruction prefix causes the next instruction to use the IX register instead of the HL register. That makes sense. HL and ...
  • 35.7k
14 votes
2 answers
578 views

What is the purpose of the "difference of absolute values" instruction?

The IBM NORC computer, among others, had an arithmetic instruction computing the difference of the absolute values of its operands (|x|-|y|, see NORC Programming Manual, page 11, opcode 28), which ...
  • 16.8k
9 votes
2 answers
1k views

Did any 16-bit or 36-bit computer instruction set ever include 4x4 or 6x6 bit-matrix operations?

Donald Knuth's 64-bit MMIX architecture includes several novel instructions that operate matrixwise on an 8x8 square matrix (MOR, MXOR). (MMIX also has instructions like BDIF that operate vectorwise ...
4 votes
1 answer
141 views

Are there any CHIP-8 games that break if `SAVE` / `RESTORE` *doesn't* change the pointer register?

The CHIP-8 instructions SAVE Vx (Fx55) and RESTORE Vx (Fx65) are originally specified to increment the pointer register I as each register is saved/loaded, so by the end of the instruction, the value ...
  • 2,583
8 votes
1 answer
185 views

Is scratchpad register 15 directly addressable on the F3850 (except as QL)?

The Fairchild F8 CPU, the F3850, has 64 scratchpad registers. The first 12 of these are directly addressable by several instructions. For example, the opcodes $CX add the contents of scratchpad ...
  • 1,419
13 votes
1 answer
570 views

What are the added opcodes for MC6801/MC6803?

What new opcodes were added to Motorola MC6801/MC6803? Background for the question, and what I've figured out so far (correct me if I'm wrong): The Motorola MC6801 (and MC6803) had an "enhanced ...
  • 1,419
6 votes
2 answers
843 views

What’s the last x86 CPU that didn’t place a limit on the size of a single instruction?

Although useless, it’s widely known the first Intel and derivative CPUs like the Z80 didn’t set a limit on the instruction size. This means that it was possible to fill the whole RAM/ROM with a single ...
1 vote
3 answers
694 views

How do multi-byte instructions work?

Let's say you have a hypothetical 8-bit processing machine with 256 bytes of memory. You want to load the value stored in memory location $f2 into a register. However, with a data bus of just 8 bits, ...
  • 341
4 votes
1 answer
892 views

6502 - AND instruction updates flags differently than other logic operations

Why AND instruction updates flags in the fetch step? Others logic instructions like ORA and EOR update flags in the same step that they update accumulator, in the decode step. Is it a bug of ...
  • 389
15 votes
1 answer
1k views

What are the "ports" used via IN/OUT, vs. the PEEK/POKE address space?

This is something of a followup to How much control of TRS-80 Model III disk drives was possible from its Cassette (ROM) BASIC? but on a more general topic: I know that PEEK and POKE enable direct ...
  • 2,711
19 votes
1 answer
3k views

How did the 6502 ALU perform a decrement?

Assuming that this diagram is correct: Instructions like INC, INX, and INY can easily perform increment using ALU sum with data on B input, 0 on A input and carry_in set. But how do instructions like ...
  • 389
24 votes
1 answer
823 views

Reconstruct the loop from "The Story of Mel"

From Ed Nather's hacker-epic "The Story of Mel" (using the original paragraph-formatting to save space in this question): The firm manufactured the LGP-30, a small, cheap (by the standards ...
16 votes
5 answers
2k views

Has there ever been a instruction set architecture that did not require instruction decoding at all?

I am studying basic principles of instruction set architectures and am considering what it would take to not have any instruction decoding at all. I.e., all the control lines of the computer would be ...
79 votes
9 answers
13k views

Why is the processor instruction called "move", not "copy"?

Many processors have an instruction called "move" (sometimes spelled MOV) which copies data from one location (the "source") to another (the "destination") in registers and/or memory. It does not do ...
  • 1,753
24 votes
4 answers
4k views

Why are branches relative in many 8-bit CPUs?

I was looking over an old article on the 6809 and was perusing the opcodes and noticed that the branch instructions came in two flavors, long and short. That sparked a memory about one of the 6502-...
42 votes
3 answers
6k views

What happened to the SEV instruction on the 6502?

The 6502 has a group of opcodes which copy bit 5 from the opcode into one of the status flags. (I know it's not implemented this way, but it looks as though the bit fields are: 2 bits to select the ...
  • 35.7k
5 votes
3 answers
432 views

In what way does the Straight-8 expand on the PDP-5?

A quote from the Wikipedia: The PDP-5's instruction set was later expanded in its successor, the PDP-8, to handle more bit rotations and to increase the maximum memory size from 4K words to 32K ...
  • 35.7k
9 votes
1 answer
584 views

SYNC and the 65CE02 instruction timing

From the Wikipedia's 65CE02 page: Internally, the pipeline of the 65CE02 was redesigned to reduce the number of cycles required to execute an instruction. The 65CE02 can recover faster from ...
11 votes
3 answers
2k views

Behavior of the zero and negative/sign flags on classic instruction sets

It seems to me that there's effectively two ways that the zero bit could work. Z is set iff the result of a computation is mathematically equal to 0. Z is set iff a bit pattern consisting entirely of ...
  • 638
50 votes
4 answers
11k views

What did the 8086 (and 8088) do upon encountering an illegal instruction?

Preface: This question does in part intersect with Use of undocumented opcodes, but targets especially the 8086 instruction handling. I was reading Tanenbaum's "Operating Systems, Design and ...
  • 611
39 votes
6 answers
10k views

Why does the 6502 have the BIT instruction?

The 6502 has a bit instruction which copies two of the bits into the N and V flags, pretends to and the byte with the accumulator, but discards the result and only affects Z. I'm having a hard time ...
  • 35.7k
13 votes
1 answer
934 views

How were Zuse Z22 Instructions Encoded?

The title says it all: How to En-/Decode Z22/Z23 Instructions? (History and Linkage: The question was raised by Wilson in a comment on my answer to his question "Why are PDP-7-style microprogrammed ...
  • 183k
17 votes
4 answers
2k views

Why are PDP-7-style microprogrammed instructions out of vogue?

DEC, and at least some of their computers, especially those in the 18-bit family and 12-bit family, had these opr instructions, which contained many bitfields which encoded something like "...
  • 35.7k
38 votes
1 answer
4k views

How did the 8086 interface with the 8087 FPU coprocessor?

The 8087 has many instructions - too many, it seems, to be encoded as part of the 8086 instruction set. How did the Intel 8086 interface with an Intel 8087 FPU that a user added? Consider the ...
  • 1,965
10 votes
4 answers
2k views

Was there a Western computer with blatantly missing instructions in the instruction set?

In the BESM-6, there is an instruction (045) to add index registers, but not to subtract them, however, there is a nearby unused opcode 047, which is made synonymous to 045 (in fairness, that's true ...
  • 16.8k
10 votes
5 answers
5k views

What was the main purpose of bitshift instructions in CPU?

As far as I know, even simple RISC microcontroller have a bitshift operator, and honestly I had to use it only once when I had to compute a division on a MCU that could not do divisions in the ALU. ...
  • 119
-4 votes
4 answers
758 views

Operating systems which have non-x86 instruction set architecture [closed]

What are the most famous operating systems for non-x86 computers? I mean, most famous OS which have different instruction set architecture. Background (to better understand my task): I ask this ...
8 votes
1 answer
696 views

How can floating point addition be so slow on a BESM-6?

In the BESM-6 technical manuals — for example, in the ALU description, page 4 — there is a table specifying min/max/average instruction latencies in clock cycles (the last 3 columns; the ...
  • 16.8k
28 votes
3 answers
4k views

Why does an instruction include the address of the next instruction on the IBM 650?

The IBM 650 seems to be a load-store machine. One advantage of a load-store machine is that the instruction can be shorter because there's less pressure to pack more information into it. But the IBM ...
  • 35.7k
10 votes
5 answers
1k views

Which CPUs had instructions leaving data registers in an unspecified state?

When an ALU performs a floating point division operation using the non-restoring or the SRT algorithm, it maintains the current value of the "remainder" (in quotes, because it is not a true ...
  • 16.8k
18 votes
1 answer
2k views

Which undocumented 8085 instructions is Steven Morse referring to in "In The Beginning"?

In S. P. Morse's 1980 allegory, "In The Beginning", he writes And Intel said, "Let there be an 8085 with an oscillator on the same chip as the processor, and let an on-chip system controller ...
  • 3,238
12 votes
3 answers
1k views

What is the instruction set of the Z4?

I am able to find a few instructions, such as: Fin (presumably "Fine", as in the end of a musical score, ends a program), Fin', (a conditional Fin), St (possibly "Start" -- the need for this is ...
  • 35.7k
8 votes
2 answers
798 views

Instruction set support for multiplication with a constant

Before integer multipliers in silicon, several cpus had some support for multiplication. For instance SPARCv7 has the MULScc multiply-step instruction (several other cpus also have this). As far as ...
  • 323
11 votes
3 answers
886 views

How to keep the instruction prefetcher filled up

My understanding is that the Intel 8088 has this buffer which reads ahead in the instruction stream whenever it has a spare bus cycle or two, so that when the time comes to execute that instruction, ...
  • 35.7k