Questions tagged [instruction-set]
For questions regarding the instruction sets of microprocessors.
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How does the LOADALL instruction on the 80286 work?
This undocumented instruction existed in the 80286 and, I believe, the 80386. I think it was added while debugging the chip, so the engineers could quickly put the processor into any state and test it ...
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Why is the processor instruction called "move", not "copy"?
Many processors have an instruction called "move" (sometimes spelled MOV) which copies data from one location (the "source") to another (the "destination") in registers and/or memory. It does not do ...
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Which undocumented 8085 instructions is Steven Morse referring to in "In The Beginning"?
In S. P. Morse's 1980 allegory, "In The Beginning", he writes
And Intel said, "Let there be an 8085 with an oscillator on the same chip as the processor, and let an on-chip system controller ...
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How were Zuse Z22 Instructions Encoded?
The title says it all:
How to En-/Decode Z22/Z23 Instructions?
(History and Linkage:
The question was raised by Wilson in a comment on my answer to his question "Why are PDP-7-style microprogrammed ...
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How did the Z80 instruction set differ from the 8080?
The Zilog Z80 microprocessor, known for its use in the ZX Spectrum, was designed to be a backwards-compatible extension to the Intel 8080 processor. It introduced several new instructions to the 8080'...
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What is the relative code density of 8-bit microprocessors?
When RAM is at a premium, as it was in the old days, a greater code density of an instruction set can be a substantial advantage.
(Click saver: Code density refers loosely to how many microprocessor ...
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How did the 6502 ALU perform a decrement?
Assuming that this diagram is correct:
Instructions like INC, INX, and INY can easily perform increment using ALU sum with data on B input, 0 on A input and carry_in set.
But how do instructions like ...
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What did the 8086 (and 8088) do upon encountering an illegal instruction?
Preface: This question does in part intersect with Use of undocumented opcodes, but targets especially the 8086 instruction handling.
I was reading Tanenbaum's "Operating Systems, Design and ...
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Why are first four x86 General Purpose Registers named in such unintuitive order?
On x86 the first four general-purpose registers are named AX, CX, DX, BX. It would be quite intuitive if their indices (those used in instruction encoding) were in alphabetical order, but instead of ...
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How did the 8086 interface with the 8087 FPU coprocessor?
The 8087 has many instructions - too many, it seems, to be encoded as part of the 8086 instruction set. How did the Intel 8086 interface with an Intel 8087 FPU that a user added?
Consider the ...
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PDP-11 instruction set inconsistencies
The wiki page PDP-11 architecture has a cryptic paragraph with no references or examples:
Inconsistent instructions
Over the life of the PDP-11, subtle differences arose in the implementation of ...
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Why did the PDP-11 include a JMP instruction?
The PDP-11's program counter was addressable in two ways: as a general purpose register or as a memory location.
Still, the PDP-11's instruction set included separate instructions for moving a new ...
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What happened to the SEV instruction on the 6502?
The 6502 has a group of opcodes which copy bit 5 from the opcode into one of the status flags.
(I know it's not implemented this way, but it looks as though the bit fields are: 2 bits to select the ...
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Why does the Z80 include the RLD and RRD instructions?
The Z80 has an instruction RLD, which apparently treats the lower 4 bits in the accumulator and the full 8 bits in (HL) as a twelve bit integer which it then rotates left by 4 bits. The carry flag ...
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Why does an instruction include the address of the next instruction on the IBM 650?
The IBM 650 seems to be a load-store machine. One advantage of a load-store machine is that the instruction can be shorter because there's less pressure to pack more information into it. But the IBM ...
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Reconstruct the loop from "The Story of Mel"
From Ed Nather's hacker-epic "The Story of Mel" (using the original paragraph-formatting to save space in this question):
The firm manufactured the LGP-30, a small, cheap (by the standards ...
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How did the Motorola MC68030 and MC68040 come to have the powerful and expensive CAS2 instruction?
The CAS2 instruction - double compare-and-swap - is an extremely powerful instruction that was coveted for quite awhile (and still is, really) for making lock-free and wait-free data structures - that ...
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What is the history of the PDP-11 MARK instruction?
The PDP-11 MARK instruction was intended to be used as part of the standard PDP-11 subroutine return convention. MARK facilitated the stack clean up procedures involved in subroutine exit.
To use it, ...
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Why are PDP-7-style microprogrammed instructions out of vogue?
DEC, and at least some of their computers, especially those in the 18-bit family and 12-bit family, had these opr instructions, which contained many bitfields which encoded something like "...
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Null-terminated strings on the PDP-7?
I came across a post that states that Unix uses null-terminated strings, ASCIZ, because it was a feature of the PDP-7. This triggered my reading on the CIS instructions in the PDP-11, but these were ...
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Origin of "arithmetic" and "logical" for signed and unsigned shifts
The assembly language for many processors use the phrase "arithmetic shift" to represent the bitwise shift of a signed value, and "logical shift" for an unsigned value. The two ...
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What is the instruction set of the Z4?
I am able to find a few instructions, such as:
Fin (presumably "Fine", as in the end of a musical score, ends a program),
Fin', (a conditional Fin),
St (possibly "Start" -- the need for this is ...
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How to keep the instruction prefetcher filled up
My understanding is that the Intel 8088 has this buffer which reads ahead in the instruction stream whenever it has a spare bus cycle or two, so that when the time comes to execute that instruction, ...
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What was the main purpose of bitshift instructions in CPU?
As far as I know, even simple RISC microcontroller have a bitshift operator, and honestly I had to use it only once when I had to compute a division on a MCU that could not do divisions in the ALU.
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Is scratchpad register 15 directly addressable on the F3850 (except as QL)?
The Fairchild F8 CPU, the F3850, has 64 scratchpad registers.
The first 12 of these are directly addressable by several instructions. For example, the opcodes $CX add the contents of scratchpad ...
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How can floating point addition be so slow on a BESM-6?
In the BESM-6 technical manuals — for example, in the ALU description, page 4 — there is a table specifying min/max/average instruction latencies in clock cycles (the last 3 columns; the ...
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