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Questions tagged [interrupt]

For questions regarding processor interrupt signals on retrocomputing hardware

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How do I wait for end-of-frame (VSYNC) on a TRS-80 models 1 and 3?

I've been looking at various documentations, and couldn't find a clear answer. I understand the Model 1 has no interrupt from the video generator, but I'm hoping there's at least a way to busy-wait ...
Cactus's user avatar
  • 2,708
9 votes
2 answers
2k views

Why does the BRK instruction set the B flag?

On the 6502, the brk instruction is a software interrupt. Like any other interrupt, it pushes the status word to the stack and then the program counter, before transferring control to an interrupt ...
Omar and Lorraine's user avatar
14 votes
2 answers
1k views

Is there any way to read current Interrupt Mode in Z80 machine code?

Is there any way to read current Interrupt Mode in Z80 machine code? Official Z80 datasheet mentions IMFa/IMFb registers which keep the mode value. Thank you
Max's user avatar
  • 285
2 votes
1 answer
225 views

What was the 6502's reset behaviour when the RDY pin was low

How does an original 6502 behave if the ready pin is being held during a reset/power-on event? Would it pause CPU start-up entirely, delaying when some or all of the 6 internal cycles are executed? (...
David's user avatar
  • 2,356
36 votes
4 answers
8k views

Did any MS-DOS program ever use the System Request interrupt?

As I remember, the SysRq key generated a special, unique interrupt (not an ordinary keyboard interrupt). It was supposed to let the user interrupt any process in a multitasking situation and return ...
Jess Fuckett's user avatar
5 votes
1 answer
578 views

Did the i186 use interrupt 6 for invalid opcodes?

I don't recall where from but at some point I was under the impression that the Intel 186 processor used interrupt 6 for invalid opcodes. However, there's the HP 95LX that uses a NEC V20. NEC V20/V30 ...
ecm's user avatar
  • 952
5 votes
1 answer
189 views

Does the PDP-8/E service an interrupt after any instruction, or after instructions not referencing memory only?

While researching this answer about incrementing the program counter, I found something I thought was a little odd in the FETCH state flow diagram, which is figure 3-8 of the PDP-8/E & PDP-8/M &...
Omar and Lorraine's user avatar
21 votes
10 answers
9k views

Was there any computer since about 1960 without interrupt support?

The invention and spread of interrupts in the 1950s is reasonably well known but I am curious: were there any systems after which didn't support them?
chx's user avatar
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11 votes
0 answers
235 views

Anyone know of older mentions of the word "trap" for software interrupts than the IBM 704 manual from 1955?

I've dug into the origin of the word "trap" in computer engineering. The older documented mentions of the term I can find, is the "trapping mode" in the IBM 704, specifically in ...
BipedalJoe's user avatar
9 votes
2 answers
2k views

ZX Spectrum interrupt handling: maskable and NMI

Is there a skeleton for handling the interrupt on the ZX Spectrum? Can I read it? I need the ZX Spectrum to handle an interrupt from a device and I have no idea where to start from. I like the idea of ...
ozw1z5rd's user avatar
  • 439
8 votes
1 answer
744 views

Z80 interrupt acknowledging

I have a question about the Z80 interrupt handling. This processor has 3 modes: 0, 1, and 2. Modes 0 and 2 are supposed to fetch something from the data bus, and a protocol exists to inform the ...
ozw1z5rd's user avatar
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8 votes
2 answers
2k views

Can the Z80 Bus Request be used as an NMI?

I was reading the Z80's official manual by Zilog, and there's a passage in the description for the BUSREQ pin that states "Bus Request contains a higher priority than NMI and is always recognized ...
aofarmakis's user avatar
5 votes
5 answers
520 views

Chaining IRQs in x86 ROM code

Objective Summary: I need to write a sleep() function to be used in 8088 (PC/XT ISA) ROM code with 1 ms resolution. Though the question can be more generalized to chaining INTs with data in different ...
640KB's user avatar
  • 1,297
23 votes
3 answers
4k views

How does the BIOS distinguish Interrupt(08h-12h) from INT instructions, vs. actual exceptions inside the CPU?

This is purely academic, out of date, out of curiosity. Let's go back to the 1990s, before Windows, when real-mode DOS programs were common. The BIOS assigned INT 08H+ for their own interrupt handlers,...
THS's user avatar
  • 333
5 votes
1 answer
597 views

Z80 CPU and nested/reentrant NMI

According to multiple documentation sources, non-maskable interrupts (NMIs) can be nested (or reentrant) in a Z80 microprocessor. This is, upon a /NMI signal pulse, the CPU will interrupt the current ...
Alvaro Polo's user avatar
2 votes
1 answer
282 views

Timer B Interrupt occurs only once

I was following this tutorial on Commodore 64 timer interrupts and tried to replicate it (except all I was planning on doing was changing the border color.) I noticed that my interrupt only occurs ...
puppydrum64's user avatar
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1 vote
1 answer
337 views

How does RETN return from NMI on the Z80 in the event of nested NMI?

I was trying to learn how the Sega Master System works. The NMI occurs when the pause button on the console is pressed. So I wrote an NMI handler that makes a beep when the NMI occurs, then waits for ...
puppydrum64's user avatar
  • 1,638
5 votes
1 answer
516 views

What kind of graphics hardware did Nichibutsu's 1985 arcade game "MagMax" use?

The arcade game MagMax by Nichibutsu came out in 1985 and features for its time an impressive 3D scrolling effect which, in my observation, is not widely discussed yet, although it should be ...
scrØllbær's user avatar
  • 1,109
15 votes
4 answers
3k views

How was the real-time clock implemented in the original IBM PC and PC/XT?

I know that the IBM PC/AT added a battery backed real-time clock chip that independently maintained time whether the system was powered or not. I've also seen many of those big DS1287 clock chips on ...
smitelli's user avatar
  • 1,769
17 votes
3 answers
2k views

Why can't I invoke the next interrupt service by incrementing the AX register after calling the same interrupt?

I have two snippets of 8086 assembly code, both of which are supposed to do the same thing: make the mouse appear on the screen. Show_Mouse: push ax mov ax,0 ;Reset Mouse int 33h ...
puppydrum64's user avatar
  • 1,638
4 votes
3 answers
363 views

What would be the value on the data bus for a Jupiter ACE with the Z80 Interrupt Mode 2?

I am writing an emulator for the Jupiter ACE. I assumed the idle bus value would be 0xFF like the ZX Spectrum. Other emulators for the Jupiter ACE seem to assume the same. If there are no peripherals ...
Kpalser's user avatar
  • 143
7 votes
2 answers
1k views

Did any ZX Spectrum clones use the Z80's interrupt mode zero?

The standard Sinclair ZX Spectrum only used mode 1 and mode 2 interrupts but the Z80 also has a mode 0 interrupt that the original Speccy never used. But there were many exotic clones of the ZX ...
hippietrail's user avatar
  • 6,654
7 votes
3 answers
1k views

How long are interrupt requests remembered on the Amstrad CPC?

I'm trying to emulate an Amstrad CPC 464. Currently, I'm working on interrupt handling and I'm wondering: Some Z80 instructions, like EI or decoding multiple consecutive 0xdd prefixes don't accept ...
mdm's user avatar
  • 497
3 votes
0 answers
290 views

How did commercial GBA games sample the button state?

For the GBA, I am under the impression that there are two ways to detect a button event: Enable IRQs and set up a handler for the button event Get a button's state (via the input bitmap) during the ...
forest's user avatar
  • 2,029
5 votes
1 answer
290 views

Chaining IRQ's with BASIC & Kernal routines turned off

Having disabled BASIC and Kernal routines I set up an IRQ to run the following code when the raster line reaches 200: .irq1 inc 53280 // change border colour // lda #$ff // clear the ...
user avatar
4 votes
2 answers
784 views

Z80: Interrupt (IM2) daisy chain for "foreign" peripherals

I'm looking for a way (apart from manually wiring up Fig.15 of The Z80 Family Program Interrupt Structure) to daisy chain "non-Z80-family" devices in an IM2 Z80 system i'm designing. So far ...
nonchip's user avatar
  • 233
12 votes
2 answers
2k views

BIOS interrupts vs Hardware interrupts

On an x86 chip running in Real Mode, interrupts are resolved with the help of the IVT (Interrupt Vector Table), which is an array located at address 0000h:0000h that consists of 256 entries, 32-bit ...
DarkAtom's user avatar
  • 2,337
3 votes
0 answers
152 views

Zenith Data Systems laptop with Timer Interrupt Error

I have an old Zenith “laptop” that runs on an 80c88 processor, and apparently was manufactured around 1985. It’s quite a beast of a laptop - size and weight, rather than computing power!. ...
RobC's user avatar
  • 99
6 votes
2 answers
592 views

Were any M68000 systems capable of generating a "spurious interrupt"?

When an interrupt occurs on a Motorola 68000-family processor, it enters an interrupt acknowledge state, which continues until one of three signals are asserted: An external device places the ...
DrSheldon's user avatar
  • 16k
12 votes
2 answers
741 views

(Lack of) identifying IRQ sources in C64 interrupt handlers

I'm trying to learn about C64 interrupt handling (with the goal of putting it in practice). My understanding is that interrupts can be triggered by different sources but there is only one interrupt ...
Zoltan's user avatar
  • 265
3 votes
4 answers
833 views

Is the ZX Spectrum multithread capable? [closed]

I know the spectrum had the IM2 mode, but can I start multiple threads running simultaneously? Like to play sounds, watch the keyboard, and other tasks who can be runned simultaneous.
Marcelo Nunes's user avatar
14 votes
2 answers
943 views

Does the Z80 allow interrupts after processing and ignoring a 0xdd prefix?

I read here that if the Z80 encounters e.g. multiple 0xdd prefixes in sequence, for each 0xxdd except the last it acts almost like a NOP, but does not allow interrupts to occur immediately after "...
mdm's user avatar
  • 497
3 votes
2 answers
358 views

What's the Motorola microprocessor with two sets of registers to avoid costly context switch?

I remember reading somewhere (maybe on Hacker News or Lobsters) that Motorola made a microprocessor some decades ago with two sets of registers. This means when handling an interrupt, it does not need ...
nalzok's user avatar
  • 131
3 votes
2 answers
559 views

6502 interrupts when RDY is low

If the NMI line goes from high to low when the RDY is low, is the NMI detected, so that when RDY goes high, NMI is performed ? Or is the NMI discarded when it occurs when RDY is low ? (In case of ...
Johnmph's user avatar
  • 389
7 votes
1 answer
413 views

Importance of obeying Apple II IRQ priority

In the Apple II, DMA and IRQ priority is determined by a daisy-chain system, in which a card may only assert an IRQ or perform DMA when all higher-priority cards allow it. I understand the importance ...
Zane Kaminski's user avatar
15 votes
1 answer
869 views

Why didn't Wozniak's interrupts work on the Apple I monitor program?

In his autobiography, Steve Wozniak recounts[1] his difficulty getting interrupts working on the 6502 microprocessor: The next step was to debug the 256-byte monitor program on the PROMs. I spent ...
snips-n-snails's user avatar
17 votes
1 answer
2k views

How does single-stepping on the 8086 interact with internal and external interrupts?

The 1979 version of the 8086 family user's manual is available at different places in the internet, see 1,2,3. It seems there is no newer version available. This manual documents the single-stepping ...
Michael Karcher's user avatar
29 votes
3 answers
7k views

What are uses of the byte after BRK instruction on 6502?

The BRK instruction on the MOS 6502 seems to be one of the more ill-documented features of the processor. The 1976 preliminary data sheet from MOS indicates that it's a 1-byte instruction using the &...
cjs's user avatar
  • 26.6k
17 votes
7 answers
3k views

8086 stack segment and avoiding overflow in interrupts

This is a followup to Could the Intel 8086 CPU have many segments in memory of the same type? In the event of a hardware interrupt or user interrupt through the INT instruction, was there a risk that ...
pjc50's user avatar
  • 1,015
3 votes
3 answers
582 views

Interrupt pin type on the 6502

I have a really basic question. I have to design an 65C02-based personal computer for a school project. I have to draw my own footprint for the 65C02. My question is what type of pin is the IRQB (...
ZaharyMomchilov's user avatar
21 votes
4 answers
2k views

Did the IBM PC use the 8088's NMI line?

As I understand it, the Intel 8088 CPU used in the original IBM PC had two interrupt lines: INTR and NMI. INTR was fed from the Intel 8259 Programmable Interrupt Controller, which handled the IRQs ...
smitelli's user avatar
  • 1,769
6 votes
4 answers
3k views

How does the Z80 determine which peripheral sent an interrupt?

My understanding of how interrupts (and more specifically, interrupt daisy-chaining) works in the Z80 is limited, to say the least, so if I get anything wrong please correct me. Anyway, let's say I ...
Jacob Garby's user avatar
8 votes
3 answers
1k views

Why do we need to acknowledge the interrupt from VIC-II?

A page on how to do raster interrupts includes the following code Irq: LDA #7 STA $D020 ; Turn screen frame yellow LDX #90 Pause: DEX BNE Pause ; Empty loop that &...
Omar and Lorraine's user avatar
3 votes
1 answer
579 views

Is it possible to switch the interrupt source of the C64 to VIC without changing the IRQ routine?

The ROM IRQ routine at $EA31 is usually trigggered by the timer interrupt 60 times a second. Is it possible to switch the interrupt source to VIC and still use the same routine? If yes, which memory ...
Peter B.'s user avatar
  • 4,387
5 votes
2 answers
363 views

Does the Intersil 6100 do interrupts differently from other PDP-8s?

As I recall, the original PDP-8 actually does a jsr 0000 when an interrupt happens, so that the interrupt service routine started at address 0001. I think that saves a few gates, since the instruction ...
Omar and Lorraine's user avatar
7 votes
5 answers
1k views

What stops an IO device from driving the databus longer than the CPU expects?

For example, consider the case of handling an INT interrupt signal in the Z80. When the CPU makes the IORQ signal active, it expects the requesting IO device to place a vector onto on the databus. And ...
Jet Blue's user avatar
  • 2,005
9 votes
3 answers
2k views

Why do they use CLI in an IRQ routine?

I am studying an FLI routine in http://codebase64.org/doku.php?id=base:fli_displayer and I noticed that the CLI instruction is being used in this IRQ routine: irq0: pha ... cli ; &...
Digerkam's user avatar
  • 301
6 votes
4 answers
1k views

Intel 8080 and Altair 8800. 256 I/O ports, but only 7 free RST (interrupt subroutines) — how does it work?

I have seen the video Altair 8800 - Interrupt Acknowledge Cycle and I have a few questions (I have read Wikipedia’s Intel 8080 article, the Altair 8800 Operator's manual, Charles Petzold "Code&...
MiniMax's user avatar
  • 295
6 votes
3 answers
467 views

What is the FPD bit on the PDP-10?

When an interrupt happens on a PDP-10, as on many other architectures you get the program counter pushed onto the stack. Actually, the program counter includes many status bits in the upper half of ...
Omar and Lorraine's user avatar
5 votes
2 answers
2k views

How can a C64 interrupt let the KERNAL keep operating?

I am working on a loading screen, and what I wanted was a simple raster trick (just change the border colour on the bottom half of the screen), and also call the KERNAL to load some more data from a ...
Omar and Lorraine's user avatar