Skip to main content
Share Your Experience: Take the 2024 Developer Survey

Questions tagged [io]

The tag has no usage guidance.

Filter by
Sorted by
Tagged with
3 votes
1 answer
203 views

Did any big-iron systems implement offloaded database IO tasks?

I think I might have a false-memory, but I remember reading about some big iron system (1970s to the 1980s, I suppose) that set database benchmark records because it delegated bulk OLTP DML and ...
Dai's user avatar
  • 823
0 votes
2 answers
360 views

Difference between the 8255 and 8042 PPIs

What is the big difference between the 8255 PPI and the 8042 PPI? (except that the 8255 has more IO) Things that I spotted: the 8042 seems to have its own clock (not using the CPU one) which seems to ...
juffma's user avatar
  • 195
4 votes
1 answer
238 views

Are there multiple models of the Intel 8089 IOP?

As far as I'm concerned there is only one model of the Intel 8089 (the D8089A-3). I am not able to find any information on this. While the 8086,8088 and 8087 use the scheme of the last number (-3 in ...
juffma's user avatar
  • 195
6 votes
2 answers
584 views

CONIN (Console In) in CP/M and "old characters" in character latch

CP/M uses CONIN to read a single character from the keyboard, and it will assert CONST to poll the status register for incoming characters. Let's assume the keyboard controller can buffer one ...
BipedalJoe's user avatar
2 votes
2 answers
272 views

How the I/O performance of legacy mainframes/minicomputers in different architectures is measured and benchmarked comparatively?

Powerful in computing power, mainframes were irreplaceable thanks to the capability of processing numerous transactions rather than doing the math. While computing power is measured in FLOPS and MIPS, ...
Schezuk's user avatar
  • 3,754
18 votes
2 answers
3k views

Why was there a need for separate I/O address space in addition to a memory address space already?

I was reading through PCI and PCIe configuration access mechanism in Chapter 3 (page 96) of PCIe System Architecture (Mindshare series). As a solution to prevent locking (in case of multiple threads) ...
analogkp's user avatar
  • 183
22 votes
1 answer
598 views

Where is Mike Lesk's (circa 1973) "portable I/O package" for C?

According to Dennis Ritchie's 1993 paper The Development of the C Language: Also during this period, the compiler was retargeted to other nearby machines, particularly the Honeywell 635 and IBM 360/...
Simon Kissane's user avatar
10 votes
3 answers
2k views

How was character data handled in Fortran IV/66?

One of the notable contributions in FORTRAN 77 was the CHARACTER data type, which made character processing quite usable. As I understand it, FORTRAN 66 (sometimes called FORTRAN IV, but they're not ...
Will Hartung's user avatar
  • 12.3k
13 votes
2 answers
2k views

If a PS/2 device on a 32-bit x86 sends a byte to the IO port 0x60 and you read it, what happens next?

I'm writing a hobby OS and the first thing I want to do is access PS/2 devices (it's a somewhat legacy, 32 bit OS, so I figured it's relevant to ask here?). I can see my PS/2 devices and I want to ...
Michael Stachowsky's user avatar
6 votes
2 answers
503 views

Flash border color during Kernal LOAD routine

I would like to use the Kernal's LOAD routine to load a file into memory, because that seems to be the easiest way to do it. However, that LOAD call is synchronous in the sense that it returns once ...
Cactus's user avatar
  • 2,708
9 votes
1 answer
2k views

Is this a bug or an allowed Pascal behavior?

Consider the following Pascal program: 1 1 PROGRAM MAIN(OUTPUT); VAR F:TEXT; I:INTEGER; 2 2 BEGIN 3 2 REWRITE(F); 4 3 FOR I := 10 TO 30 DO BEGIN 5 3 WRITELN( I, ’...
Leo B.'s user avatar
  • 19.3k
1 vote
1 answer
134 views

What kinds of input/output devices could the Electrologica X1 interface with (simultaneously)?

Here is a brief survey of the literature that I know of/have access to: The most complete description of the X1 that I am aware of is given in Dijkstra's 1959 PHD thesis, which describes in detail ...
texdr.aft's user avatar
  • 3,495
4 votes
5 answers
641 views

Are there any good resources on emulating/simulating early computing input/output?

Note: I hope this question is on topic. I'm not sure where else to put it. There are several tutorials available online for writing emulators/simulators. Unfortunately they all seem to focus on ...
texdr.aft's user avatar
  • 3,495
5 votes
3 answers
3k views

8086 duration of program

I have the following assembly code for 8086 MOV AL, [BX] OUT DX, AL The bus clock frequency is 1MHz. Access to memory is done without WAIT, and to I/O with one WAIT tick. How I can calculate the ...
gameloverr2's user avatar
5 votes
1 answer
494 views

Why is my program outputting only zeros to the data bus during I/O operations?

I'm building a breadboard Z80-based computer. As now, I have the CPU hooked up to an EEPROM and an I/O device (an HD44780 character display) with appropriate decoding logic. The ROM chip starts at ...
penguin86's user avatar
  • 145
2 votes
1 answer
315 views

READY / WAIT when reading from / writing to IO ports

During the execution of an IN or OUT instruction (so after the opcode and its single-byte argument have been fetched from memory), how does the Intel 8080 react to its READY pin going down? Is it ...
Cactus's user avatar
  • 2,708
7 votes
2 answers
1k views

Did general purpose I/O controller chips come with fewer than 40 pins?

I'm aware that 40-pins was a high-water mark for dual-inline package chips for a significant time; many CPUs of the early 1980s (8086, Z80, 6800, 6502, etc) used 40-pin packages, but no larger. ...
Kaz's user avatar
  • 8,146
15 votes
1 answer
1k views

Why did POKEing ROM addresses mask port writes?

After reading mcleod_ideafix's answer about the Inves Spectrum+'s "randomize of death", specifically his article on the subject, one thing struck me as odd. From César Hernández Bañó's research: ......
wizzwizz4's user avatar
  • 18.6k