Quoting from [here](http://www.cs.utexas.edu/users/pingali/CS378/2008sp/assignments/hw1/assignment1.html): _early versions of the MIPS processor had an "exposed pipeline" (that is, the assembly language programmer needed to know the latencies of operations and had to insert NO-OPS or other operations between dependent instructions to guarantee correctness). Later versions of the MIPS processor abandoned this idea._

The above is what I was able to find by googling "CPU with exposed pileline" (mentioning "CPU" in the search string is important). The [MIPS architecture](https://en.wikipedia.org/wiki/MIPS_instruction_set) was introduced in 1981 (unfortunately, the wiki page doesn't mention the exposed pipeline).

It is my understanding that VLIW architectures which also have an exposed pipeline, came later. Is that true? Was MIPS really the first one?