One use is as a copyright mechanism. Many distributors would steal/copy programs and sell pirate or derivative copies, by changing the text strings inside the code and reordering the blocks, it was hard to prove the code had been stolen.
Placing noops of different types you could put a signature sequence which was much easier to detect and hard to hide. A ...
The NES was also from the era where some sound and graphics resources were also executable code. (Typically, this worked the other way around. Identify a needed sound and listen to chunks of the binary to find a reasonable candidate.) Injecting NOPs can improve the look or sound derived from a section of executable.
Example: "One of the more-challenging ...
Sinclair didn't always use the Z80 for its computers. The MK14 computer, sold in kit form (like the ZX80 was), used a National Semiconductor INS8060.
The ZX range of home computers have a video display hardware that is very closely tied to the architecture of the Z80.
On the two first models, ZX80 and ZX81, the video display hardware was kept to a minimum, ...
The 6502 CPU is just one piece of the puzzle
Emulators emulate entire machines, not merely CPUs. Even the likes of QEMU emulate an entire generic computer.
It helps if you think of the Apple II and NES not as singular units but as networks of components. The CPU, graphics unit, RAM and so on all have communications to each other and do so at a very fast ...
Yes, BASIC is much slower than assembly for many operations. For an
easy example, try out this program on a Commodore 64 or emulator:
for i = 1024 to 1984 : poke i,peek(i) or 128 : next
You will see each character on the screen reverse, row by row, over
the course of ten seconds. By contrast, the exact same routine in
machine language inverts the entire ...
Setting and clearing carry, the decimal or interrupt flags is useful:
the carry flag because the 6502 offers only add and subtract with carry;
the decimal flag because it changes the mode of the processor; and
the interrupt flag because it masks or unmasks the maskable interrupt.
Conversely, explicitly setting and clearing the other flags mostly isn't ...
Like all games from that era, cheating and tables.
Two 256 byte tables and logarithms gave a 10x speed boost on multiply and divide on Commodore 64 at least.
Matrix operations using addition only for fixed known rotation rates.
Only convex shapes making hidden line removal simpler and hidden line removal meaning only half the vertices ...
Early MOS documentation (KIM-1 Programming Manual, Synertek SY6500/MCS6500 Microcomputer Programming manual, etc) states:
The BIT instruction actually combines two instructions from
the PDP-11 and MC6800, that of TST (Test Memory) and (BIT Test).
In addition to the nondestructive feature of the BIT which
allows us to isolate an ...
I'm just speculating here, but one possible reason for using a 2-byte NOP would be if you wanted to change an existing 2-byte instruction into a NOP (to fix a bug, for instance), without changing the byte count for the instruction. (An undocumented 2-byte NOP might execute more quickly than two standard 1-byte NOPs in succession.)
You might do this to ...
MADS uses * in three ways (See MADS "Manual")
Using the current assembly address for calculation of an address, i.e. the one the actual statement is assembled to.
Multiplying in expressions.
Mark the beginning of a comment (until line end)
In above listing it will be interpreted as the address the JMP instruction is assembled to, so it will form an ...
The simple answer is that early operating systems for the systems you mention did not provide those features.
Apple DOS, for example, makes no use of interrupts, and has no concept of processes or memory protection. Nor does DOS have any concept of hardware drivers, as it includes support to drive the Disk II (a deep assumption in DOS) and nothing else. ...
The instruction $89 on the 6502 is a two-byte NOP. Based on adjacent instructions in the opcode matrix, especially LDA #ii ($A9 ii), it would have been STA #ii, a store to an immediate value, which makes no sense. On the 65C02, this instruction is changed to BIT #ii, which almost behaves as a two-byte NOP. One hypothesis is that a programmer ...
An instruction set can be considered as a Huffman coding of an idealised instruction stream. So the question is really asking which CPUs have a good balance of short encodings for common tasks to longer encodings for rare tasks. However, it is not sufficient to just look at the encoding of individual instructions because a RISC instruction generally does ...
There are many answers to this and none might satisfy you.
First of all, an Emulator doesn't just do a CPU, but a machine. The same way you can't run an NES game on an Apple II. So while one may do multiple ones, different can do the hob as well.
Furthermore, there are different target platforms. Linux isn't Windows which again isn't MacOS and so on. Like ...
The 6502 had 16-bit addressing but only an 8-bit adder. For an indexed load or store, the index register had to be added to the base address in two steps. As an optimization, the 6502 will load from memory as soon as the first part of the add is complete. If the add didn't cause a carry out, the loaded value is kept. If it did cause a carry, the value is ...
First, for Commodore's part, it should be obvious the reason for choosing the 6502 microprocessor for all their 8-bit machines (notwithstanding the dual-processor CBM 9000 and C128) - Commodore owned MOS. Jack Tramiel was very focused on vertically integrating his manufacturing, which basically assured Commodore's use of MOS CPUs and support chips. Since ...
I'm having a hard time picturing a use for this [BIT]
It's mainly an I/O issue.
The 6502 is in many ways designed especially for control/embedded applications and BIT is a part of this. 6500 specific IO-devices are designed to report any service conditions on bit 7 (and 6). For example the 6522 will set bit 7 of the Interrupt Flag Register when an ...
For "home" computer systems such as the Apple II, the "operating
system" wasn't anything like a modern one with processes and device
drivers and so on; by the standards of modern OSes there wasn't really
one at all.
As a warning: all these explanations (long as they are) are for the
most part considerably simplified. This answer is intended to give you
It is all about making one of the most important instructions as performant as possible, while keeping everything manageable for tools at the time (plus a little bit of dogma). The branching is thus the most optimized instruction of the whole 6502 design.
In addition, long branches are not really in demand (*1). Of the 116 branches used in the ...
Both processors are cacheless. So the process is fetch instruction, decode instruction, execute instruction, forget what you saw. That provides a first line of comparison.
The Z80's fastest memory fetch — the first half of an operation fetch — takes two cycles. That's always paired with another two cycles for refresh though, so the shortest instructions are ...
On the BBC Micro, the byte after the BRK instruction held the error number, followed by the error message string terminated with 0x0D. CALLing the address of the BRK instruction would cause an error to be raised.
Update with example, as a runnable BBC BASIC program:
10 DIM b% 32
20 ?b%=0: REM BRK
30 ?(b%+1)=42: REM Error number 42
There is simply no need for setting Overflow. The same is as well true for Negative/Sign and Zero. No operation will be influenced by any of them, it's only used to signal an overflow during ADC and SBC (well, and BIT for testing bit#6).
In fact, the question is rather, why there is a CLV present, as there is no reason, within the boundaries of the ...
If you look at the screen clear code in the Applesoft BASIC ROM, you'll find this:
f3f6 lda $e6 ;put base address of current hi-res page
sta $1b ; into $1a/1b (will be $2000 or $4000)
f3fe lda $1c ;get color value
sta ($1a),y ;store it in frame buffer
jsr $f47e ;...
The code you've posted:
loads the immediate value 0 into A;
loads the immediate value 3 into Y;
then compares the 0 in A to whatever is in memory at the address you've given the label Y.
There are no register-to-register comparisons on the 6502.
The designers figured that you'd use X and Y for looping, indexing etc, and use A for adding and subtracting, shifts etc. So they saw a need for INX and INY, but didn't see a enough of a need for an instruction to increment or decrement the accumulator.
That's also the reason why X and Y cannot participate in many ALU operations, like adds, shifts, and ...
The MOS 6502 (1 MHz) was introduced in 1975 for a price of $25. Then in 1978 MOS agreed to sell the 6502 (1.79 MHz) and an IO chip to Atari for $12 per set (because the production cost was $4).
In 1977, the Zilog Z80A (4 MHz) was $65 for the ceramic package and $59 for the plastic version.
A good example would be reading from the floppy drive on the C64. The incoming clock and data signals of the serial bus are (perhaps not accidentally) wired to bits 6 and 7 of port A on CIA#2, appearing at $DD00.
samples both inputs and stores them in the N and V flags. Jumping back conditionally with
waits while the clock is low, as ...
To a certain extent you can guess the number of cycles by counting the number of memory accesses.
A 2-byte instruction will take a minimum of 2 cycles because you need to read 2 bytes. If the instruction needs to read or write a data byte add another cycle. For example, a zero-page read is a 2-byte instruction, but in addition to reading the instruction ...
Without issuing a CLI, no further interrupts can occur (until EOI, at least, where flags are restored by the RTI instruction). As this is a raster interrupt, you need to acknowledge that as well for another one to happen, which the seemingly benign $D019 manipulation achieves earlier in the interrupt handler, cf. the linked FLI routine.
In this specific ...
But how instructions like DEC, DEX and DEY works ?
By adding $FF provided by the precharged internal data bus to the register content.
The internal databus is precharged with $FF during PHI2 (*1)
During the next phase it's loaded into the B register (signal DB/ADD)
At the same time the index register is transfered via SB (*/SB) to the A ...