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If the SB/X (load) signal and X/SB (bus enable) signal are both asserted at the same time, what happens? You mean beside the fact, that it would need a useful instruction based on that function? Since read and write port are different, X would be loaded with itself. A quick look at the Visual6502 graphics seem to support that.


The 6502 only uses one phase of the clock for memory accesses. The other phase can be used for access to memory for other purposes. The Apple II used this technique. It did not use READY (although that was available on the peripheral bus). This idle phase of the clock was used for providing the data for the the display at the required refresh rate. By ...

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