The MOS MCS6500 microprocessor family datasheet from May, 1976 indicates that:
"All versions of the microprocessor are available in 1 MHz and 2 MHz maximum operating frequencies."
The document is archived here: http://archive.6502.org/datasheets/mos_6500_mpu_preliminary_may_1976.pdf
Does the 6502's TXS and TSX affect flags or not?
TSX does affect N and Z
TXS does not affect any flag
In general all instructions moving data to one of the Registers (A, X, Y) do set N and Z according to the data moved.
Excerpt of the instruction list from the 1976 data sheet on page 6:
The CPU needs to do an addition of the 2-byte address after the opcode and the 8-bit unsigned displacement from X or Y register.
Since 6502 addresses are always stored as little-endian, the CPU gets the lower byte first. During the time it reads the following higher byte, it simultaneously performs addition of the lower byte just read and the contents of the ...
TL;DR: It's always included.
If you compare the timing of memory writing using Absolute,X (ASL, DEC, INC, LSR, ROL, ROR, STA) or Absolute,Y (STA) with their counterpart using Absolute (without indexing), you'll note that the additional cycle is always included. It's only 'optional' for reading instructions.
Example from the (original) table (abreviated):
An engineer who worked at National Semiconductor back when reverse engineering was legal described a conference room wall covered with a patchwork of photos representing an entire Intel microprocessor. They visually extracted the circuit from the image.