The original 65816 layout was done by hand and was not amenable to high speeds. In particular, REP/SEP (perhaps PLP as well) instructions didn't complete in 3 cycles when overclocked. (Even today, the data sheet notes, "the MX [pin] output is invalid during the instruction cycle following REP, SEP and PLP instruction execution").
The Transwarp GS ...
The 65816 physically has an 8-bit ALU, though many of the internal registers are now 16 bits wide. It therefore takes an extra cycle to perform each ALU operation in 16-bit mode, and this helpfully gives the needed time to get the extra data over the data bus (which remains very simple to interface).
There is no part of the core where a 16-bit data bus is ...
Keep in mind that because the memory in banks $E0 and $E1 are used as the 128K of memory in 8-bit mode (yeah, it's counterintuitive), they are controlled by the MEGA II chip, which is in essence an Apple IIe on a single chip (aside from processor and a few other support circuits). Any time access happens within the MEGA II's domain, the system has to slow to ...
JSR works how you think — the program counter will head off to 80fa — but the SNES doesn't. The two most common memory mappers both mirror what's at $00xx at $80xx.
So when the processor reads from $80fa it gets the same thing as if it read from $00fa.
Per the linked article, in a 'HiROM' (i.e. one of the two common types):
Banks $80 - $FF can also be ...
The 65816 is intended as an upgrade path to existing 6502 customers. Keeping it 8 bit was a sensible decision from a user view as it offers
Easy upgrade of existing designs
Fully compatible with existing software
Standard 40 pin package needs less thru holes and offers cheaper handling
Only a single latch is needed to use the extended address range
I am not an expert on this processor or its history but this sounds like the sort of silicon bug that I have had to deal with on many processors over the years. It is often the case that there are timing problems with early versions of the silicon for a given processor that then require a software workaround. These are normally detailed in a processor ...
The advantage of the 8-bit external data bus and multiplexing of the
top 8 bits of the address bus in the first release of the 65816 seems
clear. There were actually two versions of the chip: the W65C816S as
described in the question and the W65C802. According to
[The] 65C802...was identical inside to the 65C816. Both were
produced on the ...
Are old 65C816s TTL compatible?
If their Vih is 2.0v, they are certainly TTL-compatible.
Was there some kind of change?
All WDC chips seem to be verilog-reimplemented, so when they synthesized them into netlist, they've intentionally dropped TTL-compatibility of IO-pins.
The reason for that might be the need to have chips working in 1.8V..5.0V range (...
I guess the answer is simple: there is no need for such a version of 65C816 nowadays. The Western Design Center (WDC), the 65C816 manufacturer, focuses on IPs and IoT things. I guess the "new 65C816" production is a kind of nostalgia for them. Chip and package revision has no clear business case, IMHO.
Another question is "why there was no 16bit data bus ...