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When 8086 and 8088 actually sample READY to determine if wait states need to be inserted?

Adding to Raffzahn's detailed answer: The main takeaway is: Nothing actually happens during T3 or Tw. There is stuff happening around the time when T2 is over (like the processor outputting valid data ...
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When 8086 and 8088 actually sample READY to determine if wait states need to be inserted?

So, if I want to insert a wait state, do I need to keep RDY inactive at the end of both t2 AND t3, or is it enough to have deactivated only at the end of either t2 OR t3? Let's dissect the text while ...
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