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54

Illegal opcodes were just instructions that hadn't been fully defined by the chip designers – a little like Undefined Behaviour in C, but much more predictable. Many people called these "undocumented instructions", because they functioned just like ordinary instructions, on the particular versions of the particular chips on which they are found. There was no ...


45

It might be better to think about it this way: On the 80186 and above, a new thing was defined called an "illegal instruction", and this new thing came with a new behavior -- a #UD exception that was generated when one was encountered. Before the 80186/80286, there was no such thing as an illegal instruction, just undocumented ones. Your question then ...


38

Worshipping at the altar of color clock Back in that day, everything was built around the NTSC color clock frequency of 3.579545 MHz. Everything from the Atari VCS to the C64 made ample use of it, because some iteration of your product would inevitably need to talk to a commodity color NTSC display operating at that frequency. This will come up; so FYI ...


33

According to Wikipedia, a number of reasons contributed to IBM’s using the 8088 instead of the 8086: Intel offered them a better price for the 8088 and was able to supply more of the chips; the 8-bit data-bus meant that IBM could use a modified 8085 design (the System/23) instead of coming up with a new 16-bit design; it also meant that IBM could use more ...


33

But why was the 8087 designed such that it needed a special socket? Because the 8087 is a processor EXTENSION, not another CPU. The 8087 has, except for a few lines, exactly the same signals and pinout as the 8086/88. The socket is, except for 4(?) lines, a one-on-one duplicate of the CPU socket. This includes signals that need to be connected between both ...


30

Your code runs through the data ("Hello World" string) interpreting it as (nonsense) machine code - and very probably crashes before it even reaches the jmp instruction. You need to move the jmp instruction to before the string.


28

For many kinds of parts, there's a substantial gap between specified maximum/minimum timings and typical timings. The 8088 specification requires that the clock be high for a minimum of 69 ns every cycle and low for a minimum of 118 ns. Dividing a 14.3818 Mhz clock by three yields a high time of 69.5 ns and a low time of 139.1 ns, satisfying both ...


25

This is not a complete answer because it doesn't answer what the exact cost savings were, but I think it's worthwhile to have an informed primary source for the claim that there were cost-savings and commodity-components motivations behind IBM's choice to use the 8088 instead of the 8086. Peter Norton, PC guru and DOS programmer extraordinaire, writes in his ...


21

Your reading is correct, SP is undefined after a reset and the stack has to be set up appropriately by the initialisation code before it can be used. Interrupts are disabled after reset so there’s no risk of the stack being used by an interrupt (short of a NMI, but you’re in dire straits if that happens anyway at this stage). The book I’m looking at just ...


19

Quartz used in colour TVs such as 3.579545MHz or 14.31818MHz used to be much cheaper than other frequencies. It was important for home computers and game consoles (8/16 bits), which used the same quartz for video and the CPU, keeping everything synchronous. It was far less siginificant for rather expensive computers such as IBM PC which didn't need to ...


16

In a 100% compatible PC, NMI is used only to communicate unrecoverable errors — normally a RAM parity failure, but possibly something else, which should reveal itself via one of the system control ports, specifically you should check: Port A: b4: watchdog timer status; Port B: b6: channel check failure (i.e. a bus failure, likely a peripheral device); b7:...


15

All right, I was curious what actually happened when you tried to execute that code. Because it crashes, obviously something is wrong, but what exactly is wrong. After some digging, I finally found a machine on PCjs.org which both boots to a usable command line, and has sufficient hardware to be able to run DEBUG with good results. Start at the Windows 95 ...


13

Caveat: I can't confirm that this works acceptably, as I haven't been able to find any references to anyone who has done it, but by reading the datasheet of the 80C88 it seems it should work there, and it may also work on an original HMOS 8088, but that's less certain as the HMOS design wasn't static (although it could work at relatively slow clock speeds, e....


13

My understanding is that the Intel 8088 has this buffer which reads ahead in the instruction stream whenever it has a spare bus cycle or two, so that when the time comes to execute that instruction, if you're lucky, that instruction doesn't need to be fetched from DRAM because it's already done for you. The buffer isn't some kind of optional read ahead,it ...


12

8-bit data bus designs were generally dramatically cheaper than 16-bit designs because they required half as many RAM chips: DRAMs of the time conventionally stored a single bit per address. So an 8-bit machine needed eight of them to populate a memory region. A 16-bit machine needed sixteen. The 8088 has an 8-bit data bus whereas the 8086 has a 16-bit data ...


12

As indicated by e.g. this description of the Phoenix BIOS, possible NMI sources are Memory parity errors x87 Coprocessor errors I/O card NMI (for whatever reason the I/O card decides to invoke it) DMA bus time-out errors (AT only) Additionally, the Programmable Interrupt Timer (PIT; 8253 or 8254) could generate an NMI using a watchdog and possibly also on ...


11

In general: memory needs stable address for a while. So the real access time is "time to address available + memory access time". If you use the CPU with a full address bus (Z80, 6502, ...), it can expose the whole address in one cycle, wait only "memory access time" interval, and you can read. On the other hand, let's take the 8085 CPU with a multiplexed ...


10

On the IBM PCJr, the NMI was used by the keyboard device to signal the CPU. (Source: “The Peter Norton Programmer’s Guide to the IBM PC”, chapter 3, under “Changing Interrupt Vectors” while discussing CLI)


10

It's simply how the 8086 works. it's a straight 16 bit CPU, isn't it? The CPU sees memory not as an 20 bit address space, only the BIU does (*1) when generating an access, but a 16 bit segment number, in CS, and a 16 bit PC in IP. The BIU uses a result derivated from CS and IP to access memory. When fetching instructions (without an MMU like in the 286) the ...


9

TLDR: Yes, it would have been possible to extend it up to 22 bit with minimal changes, 21 or 23 bit by moving two 8086 specific signals and 24 with breaking 8086/88 hardware compatibility. The Long Read As usual with What If questions, there is a huge area of possible answers. Same here. But I think we can concentrate on two issues: Changed packaging and ...


9

One thing to note – the 8088 registers are made from dynamic memory cells – they have to be refreshed. This was unexpected (at least to me), Same to me. And I guess to anyone else as well. Ken Shirriff's analysis of the 8086 registers clearly shows that they are not dynamic, but static, using the same inverter loop as the 8080 already did (and essentially ...


8

The original IBM 5150 Personal Computer (the IBM PC) connected the Non-Maskable Interrupt to the I/O Check signal, which could be driven by an add-in card, or by the on-board memory. If the systems memory detected a parity error, it would trigger a NMI, and the systems software would halt the machine and display an on screen error. You can read about this in ...


8

Will the circuit work properly if the processor and support chips are running at different speeds Short answer: No, as they usually never ever run at different bus speeds.Mixing various speed ratings just means that the system at whole should not run faster than the slowest one. Long Answer: Speed of classic CPUs like Z80 is the speed rating for the bus. ...


8

Yes, it might seem somewhat odd that Intel added extra logic to set the segment registers but not not the stack pointer; this means that even though you don't need to set up both the stack segmeent register SS and the stack pointer register SP to have a working stack, you still need to do some setup. The decision to set the segment registers at start had a ...


8

Of course, you don't need 8284 to let your 8088 run. First let see what tasks 8284 does, according to its datasheet http://www.ndr-nkc.de/download/datenbl/i8284a.pdf: It makes clock for 8088 of special shape like 1-0-0-1-0-0-... where the repeating frequency matches the specified 8088 frequency (2 to 5 MHz, according to this http://www.ndr-nkc.de/download/...


8

The 65816 does the same thing; the most-significant 8 address bits are multiplexed onto the data bus pins during the Phi1 half of each clock cycle, and it reverts to being a data bus during the Phi2 half. The WDC datasheet illustrates a simple external logic circuit which latches the address bits and isolates the data bus pins from a device responding ...


7

The 8088 and 8086 are microcoded CPUs, and need multiple cycles to execute each instruction. The fastest instructions take at least 2 cycles to execute, and most take much longer. Any instruction that accesses memory takes at least 8 cycles, and often more like 15-20. On the other hand memory accesses occupy the bus for 4 cycles. It therefore follows ...


7

To understand this, you need a general idea of how processors work at the raw hardware level (or at least how they worked before the concept of microcode was developed). Basically, as the processor would read the bytes of a single assembler language instruction, those bytes would be fed as an input to a network of logic gates called the instruction decoder;...


6

[This Answer focuses on the reason why RAM at low address and ROM at high address, as the usual ramblings about the 640Ki border have been made in other places an amasse (*1)] Why was the arrangement chosen with RAM in the first part of the address space? It's the way Intel laid out the 8086. The CPU starts execution at FFFF:0000, thus ROM had to be up ...


6

On the 8088 (which was used in the original IBM PC and early clones thereof), but not on any of the other processors used in subsequent machines, a typical two-byte instruction will take eight cycles to fetch and 2-3 cycles to execute. Because of this disparity between instruction-fetch time and execution time, the memory bus will be almost never be idle ...


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