35 votes
Accepted

Was the first ARM "processor" a BBC BASIC program?

Per Sophie Wilson: To prove that [Steve had] designed the microarchitecture correctly, he wrote, in BBC BASIC, a model of the microarchitecture. To prove that I'd designed the architecture ...
Tommy's user avatar
  • 36.9k
24 votes
Accepted

Did any early RISC OS precursor run on the BBC Micro?

This page describes one of the prototype A500s used by Paul Fellows (who led the team in charge of developing Arthur, the operating system which eventually became RISC OS). Paul Fellows himself said ...
Stephen Kitt's user avatar
12 votes

Has there been any effort to research the undocumented Thumb instructions of ARM7TDMI?

The Thumb instruction set is a compressed form of a subset of the full-size ARM instructions. As part of the fetch unit, there is a decoder which expands each 16-bit Thumb instruction into the ...
Chromatix's user avatar
  • 16.8k
12 votes

Why isn't the approach to lower power CPUs guided by design rather than accident?

The question statement is faulty. The approach to low power CPU design is guided by tools. Today. However, those tools did not always exist, or, when they eventually did exist, were too expensive ...
hotpaw2's user avatar
  • 8,183
11 votes
Accepted

Would compare-and-branch have added an extra cycle on ARM-1?

If I remember rightly (I worked at Acorn during the period ARM was designed and built, but I'll admit my memory for casual conversations from that time is far from perfect) the argument was that the ...
Graham Toal's user avatar
10 votes
Accepted

How fast did the ARM-1 access memory?

[Partial answer about how it supports FPM RAM - I still need to look up the manual for timing details] Support for (Fast) Page Mode RAM (*1) The CPU supports N and S-cycles (ARM lingo) or Non-...
Raffzahn's user avatar
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10 votes
Accepted

History of ARM Linux and FPA

It seems FPA itself was pretty short lived. From the ARM Linux mailing list (2004): There were only few devices which contained the FPA (ARM7500FE which is a complete system-on-chip, and FPA11 as ...
Igor Skochinsky's user avatar
10 votes

Would compare-and-branch have added an extra cycle on ARM-1?

Yes, it would add a cycle. How do you branch on ARM? add pc, pc, #8 That's a bit of an over-simplification, but the point is that ARM was meant to be purely orthogonal, that is, the program counter is ...
Renee Cousins's user avatar
9 votes

Is the Raspberry Pi Model B (2014) technically inferior to an original Xbox (2001) in compute power/specifically for emulators?

The original Xbox has a 733MHz Pentium 3 CPU, coupled to a GPU that is essentially an Nvidia Geforce 3. They share a 128-bit DDR memory interface that supports 6.4 GB/s bandwidth. The original ...
Chromatix's user avatar
  • 16.8k
9 votes

What are the “building bricks” of ARM’s design that this magazine article is referring to?

Such short and rather terrible wording leaves a lot to be desired. In addition it's noteworthy that the article is most likely not well researched, as it states that only IBM has used RISC in an '...
Raffzahn's user avatar
  • 223k
9 votes

Would compare-and-branch have added an extra cycle on ARM-1?

Remember that classic AArch32 code has conditional execution of most instructions, which more or less demands a condition code register in simple implementations. Once the ARM designers had included ...
John Dallman's user avatar
  • 13.2k
8 votes

Was the first ARM "processor" a BBC BASIC program?

This isn't really an answer to the question, but the comments repeatedly talk about Sophie Wilson's claim to be able to execute 100k+ ARM instructions per second. This is an impossibility on any ...
JeremyP's user avatar
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8 votes

History of ARM Linux and FPA

My experience with ARM Linux was that it was typically used for embedded systems which were not expected to routinely carry an FPU of any kind, with the notable exceptions of Android phones and the ...
Chromatix's user avatar
  • 16.8k
6 votes

What sort of SBC is in the C64 Maxi?

THE C64 Maxi Specs CPU: Allwinner H3 Quad-core Cortex-A7 @1.29GHz GPU: Mali400MP2 GPU @600mhz 256MB Memory 2GB FMND2G08U3J NAND Chip From here.
spannernick's user avatar
6 votes
Accepted

What sort of SBC is in the C64 Maxi?

Per a forum post: THEC64 Mainboard is based on this development board Rocket64 ... ROCK64 is a credit card size 4K60P HDR Media Board Computer powered by *Rockchip RK3328 Quad-Core ...
Tommy's user avatar
  • 36.9k
6 votes

Why didn't the Acorn Archimedes support general purpose co-processors?

Acorn's BBC Micro series is well known for the range of add-on processors ... ... however, other Acorn computers (the Atom, the Electron and the ABC range) did not have such an interface. So the ...
Martin Rosenau's user avatar
6 votes
Accepted

Did the ARM-1 really outperform the 387?

The answer is no. Finding numbers for the 387 is trivial, googling "387 whetstone test" brings you right to a great page that gives you a number of 5.68 MWIPS for the 386/387 at 40 MHz. ...
Maury Markowitz's user avatar
5 votes

Did the ARM-1 really outperform the 387?

I suspect the difference may lie in the floating-point formats. BBC Basic for the Archimedes used a 5-byte Microsoft format that could be noticeably quick in software, even on the 8-bit BBC Micro, and ...
John Dallman's user avatar
  • 13.2k
5 votes

How fast did the ARM-1 access memory?

The inverse perspective is to consider that ARMs were optimised for relatively slow memory (FPM DRAM), compared to contemporary pure RISC designs such as SPARC and MIPS which were designed for high ...
Grabul's user avatar
  • 3,657
5 votes

Did any early RISC OS precursor run on the BBC Micro?

When a second processor (or "co-processor") was used through the BBC Micro's Tube, the Beeb's internal CPU and RAM was used for display and I/O purposes, whereas the main program code would be run on ...
Kaz's user avatar
  • 8,096
5 votes

Has there been any effort to research the undocumented Thumb instructions of ARM7TDMI?

Undefined instructions are those not understood by the main ARM CPU core. If there is also no coprocessor that understands them, then an undefined instruction trap is executed to allow for software to ...
Justme's user avatar
  • 32.1k
5 votes

Would compare-and-branch have added an extra cycle on ARM-1?

The ARM1 CPU core was tightly coupled to the memory interface - it was designed to be as efficient as possible when paired with FPM DRAM, and no consideration was given to performance with a cache or ...
Simon Farnsworth's user avatar
4 votes

Why didn't the Acorn Archimedes support general purpose co-processors?

The original BBC Micro was designed very quickly and was subject to internal debate over its processor; the 6502 was already seven years old, and the tube appears to have been a compromise: they would ...
Tommy's user avatar
  • 36.9k
4 votes

Why isn't the approach to lower power CPUs guided by design rather than accident?

It is, as the citation already points out, if you use professional tools. Keep in mind that the first ARM developments should be better described as a hobbyists aproach. They wrote their own tools on ...
Raffzahn's user avatar
  • 223k
4 votes
Accepted

Differences between normal ARM7TDMI and ARM7TDMI used in GBA

Well, if it's an ARM7TDMI, then it's an ARM7TDMI - what else? ARM7 - 32 Bit base architecture with T - Thumb instruction set, therefore an ARMv4T micro architecture, so no more 26 bit addressing. D ...
Raffzahn's user avatar
  • 223k
4 votes

Is there a list of the differences between the various ARM architectures?

Unusual complexities The project that prompted the question is equivalent to writing a compiler, but an unusual degree of control over the generated code is desired. You may find some of the ...
John Dallman's user avatar
  • 13.2k
4 votes

Why didn't the Acorn Archimedes support general purpose co-processors?

Three contributory reasons: After the BBC Micro, Acorn were using their own processor They didn't need hardware to support other platforms Microsoft Windows hadn't cornered the market yet Using ...
Kaz's user avatar
  • 8,096
4 votes

Would compare-and-branch have added an extra cycle on ARM-1?

The CDC 6400 series of supercomputers, developed by Seymour Cray, are considered some of the earliest RISC-like architectures, having been released in 1964. These used compare-and-branch instructions....
Davislor's user avatar
  • 8,686
4 votes

Would compare-and-branch have added an extra cycle on ARM-1?

It's not very RISC purist; the designers seem to have been happy to make an instruction do more than one thing, Erm, RISC isn't about doing only one thing, RISC is about not doing complex stuff. RISC ...
Raffzahn's user avatar
  • 223k
3 votes

Has there been any effort to research the undocumented Thumb instructions of ARM7TDMI?

After the 8 bit processors (6510, Z80 & so on), the decode units tend to do one of 2 things. They either map illegal op-codes to become NOP instructions (as the 65C816 did) or trigger an exception....
Sean's user avatar
  • 71

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