Using INT comes not only natural due the way the 8086 is designed, but was as well intended by Intel as OS entry point, much like a Supervisor Call (SVC) on /360 type mainframes:
(Excerpt from the October 1979 Intel 8086 Family User's Manual page 2-28.)
Software-initiated interrupt procedures may be used as service routines ("supervisor calls&...
Yes, BASIC is much slower than assembly for many operations. For an
easy example, try out this program on a Commodore 64 or emulator:
for i = 1024 to 1984 : poke i,peek(i) or 128 : next
You will see each character on the screen reverse, row by row, over
the course of ten seconds. By contrast, the exact same routine in
machine language inverts the entire ...
Besides the matter of semantics and personal taste, there’s a much more practical reason: some instructions sets claim to be copyrighted, as the Wikipedia Z80 article states:
Because Intel claimed a copyright on their assembly mnemonics, a new assembly syntax had to be developed for the Z80. This time a more systematic approach was used.
So, I think the ...
why did high-level language compilers start targeting assembly language rather than machine code
Well, the answer is probably: to avoid developing a high level language to binary converter for each language.
Issuing assembler text is much easier than issuing binary directly for at least 3 reasons:
writing text is easier than writing binary. The compiler ...
Yes: The Apollo Guidance Computer
Uodate: Computers in Spaceflight: The NASA Experience confirms that unit testing was performed on the Apollo software:
The simulations followed individual unit tests and integrated tests of portions of the software. At first, MIT left these tests to the programmers to be done on an informal basis. It was very difficult ...
Because "move" is the typical necessary function
It isn't always this way, of course, but especially with earlier CPUs, there were limited destinations for data from a particular operation - e.g., arithmetic results could only be in certain registers. Or in the other direction, certain functions could only operate on a few locations, typically registers or ...
It is all about making one of the most important instructions as performant as possible, while keeping everything manageable for tools at the time (plus a little bit of dogma). The branching is thus the most optimized instruction of the whole 6502 design.
In addition, long branches are not really in demand (*1). Of the 116 branches used in the ...
This is a frame challenge answer.
The Burroughs Large Systems B5000 was specifically designed for being able to run programs in high-level languages (meaning COBOL, ALGOL, FORTRAN), multiprocessing, virtual memory. It had tagged memory, and builtin concurrency and multiprocessing.
The feature relevant to this particular question, is rather lack of a ...
The designers figured that you'd use X and Y for looping, indexing etc, and use A for adding and subtracting, shifts etc. So they saw a need for INX and INY, but didn't see a enough of a need for an instruction to increment or decrement the accumulator.
That's also the reason why X and Y cannot participate in many ALU operations, like adds, shifts, and ...
The PDP-8 had only 8 kinds of instructions, but one of them was "microcoded" operate command: Different bits in this command would turn on different operations, which could be combined. Here's a list of the first group of such commands:
7000 NOP no operation
7001 IAC increment acc
7002 BSW byte swap (-> rotate twice)
7004 RAL rotate ...
If there are two consecutive bytes of RAM one can write at a known address, one could store the byte values E1h, E9h [POP HL / JP (HL)] at that address and then CALL it to place the address following the call into HL. Alternatively, if those byte values appear at some known address in ROM one could simply call that address likewise. There isn't any way to ...
It's all about getting systematic, easy to memorise mnemonics, which may reflect some underlaying structure, but most important ease practical use. Exact language is not always a handy one - except you're asking a lawyer :)
So why call the instruction "move"?
Oh, the age old copy-vs-move question. A beloved friend :)
There are many different, ...
According to this answer gcc does this because of the proliferation of different object file formats: x86-64 processor alone uses ELF, PE/COFF, MachO64.
But other compilers (e.g. clang) go straight to object files without using an intermediate assemble step, so I would disagree that an assemble step is "now ubiquitous".
I'm working on implementing the instructions of the z80 chip inside a gameboy for an emulator.
Well, I guess that's the most important point here:
The Gameboy doesn't feature a Z80, but an independent 8080 descendant.
Using a Z80 opcode table will not get you anywhere.
It's LR35902 CPU (*1) is, like the Z80, based on the 8080 with some extensions. The ...
Most implementations of BASIC for 8-bit home computers were interpreters, and in that sense they're similar to the standard versions of Python. You could typically expect simple programs to run 100 times slower in BASIC than in assembly of ordinary quality.
However, it would normally take much less time to write that program in BASIC than in assembly. For ...
Early Unix C compilers were actually a pipeline, preprocessor | compiler | optimizer | assembler > abc.o. The optimizer was an assembly optimizer, doing things like fixing up things that the compiler took the easy way on, like subroutine entry and exit, and deciding between a short or a long jump (PDP-11s had short conditional branch instructions). Having ...
[Preface: This question is not only quite broad, but as well rather opinion bases. After all, what is 'unusual' depends a lot on personal experience and preference. To me for example GNU assembler's reversion of target and source is quite unusual.
Having said that, I feel the question gives a great chance to create some overview]
As I understand it, the ...
On the 6502, the designers did this for efficiency. This is documented
in the original MCS 6500 Microcomputer Family Programming
If one considers that the instruction JMP required three bytes, one
for OP CODE, one for new program counter low (PCL) and one for new
program counter high (PCH) it is seen that jump on carry set would
also require ...
As I mentioned in my comment, IBM's BIOS also used interrupts for service dispatch when it could have easily chosen a well-known address as a ROM entry point (such as how a soft reset was programmatically available by jumping to FFFF:0000). I'm speculating, but Microsoft might have been following IBM's lead.
Also, triggering an interrupt only takes two ...
Horizontal Microcode works exactly as you describe - one bit for each possible internal control line (Vertical Microcode saves instruction bits by encoding sets of N mutually-exclusive control lines with log(N) bits, with appropriate demultiplexers in place). In theory one could use this as the primary instruction level, but of course it would be very ...
Where would this 'jump table' live?
As I understand it, the use of a pure trap-based mechanism for calling system services removes the need for user programs to have knowledge of supervisor program layout. For the latter case, either (a) the table is at a well-known address that will never change, or (b) you need linker technology to include a system ...
You seem to be proposing a custom HDD "driver" that would image the HDD block-by-block by sending those blocks across a serial port to some sort of process running on your modern computer that assembles the blocks into an image file. This could be error prone and time consuming to implement.
An alternative suggestion is to use a legacy DOS Utility, such as ...
(Preface: The question is a bit misleading, as many of the conditions implied are not well defined. See below)
First candidate: Transport Triggered Architectures
Transport Triggered Architectures are not only a special case of single instruction architectures, but should this the 'no decoding' requirement quite nicely. Its only instruction is to transfer a ...
SHARC and Blackfin architectures processors are said to have "rich algebraic assembly language syntax" and are unsual in their own way. The syntax is somewhat C-like
.VAR buffer3[ 0x100];
[I1] = R0;
R1 = 0X1234;
LSETUP (begin_loop, end_loop) LC0 = P1;
R1 *= R2;
R2 = [I0++];
Prior to the creation of C, was there any unit-testing? Did any assemblers include a testing a framework?
Erm. There is no specific relation between C and testing. C as a language doesn't feature any mechanics for (unit) testing. Testing was and is a distinct item in its own right. Like for many other components of development, more generic tools and ...
Was there any Unit-Testing prior to 1972?
Yes there was. Only a fool would put a system together out of untested and undebugged parts and then try to make the system work. No framework is needed: you write some code, you test it in isolation: that's unit testing by original definition. Now you can combine your units into the next level of thing.
In the ...
Preface, this is not really how RC.SE works. If you're looking for someone to design your hardware or write you a program, there are many sites out there where you can put a reward for someone taking the job. RC.SE is about answering your questions, as detailed as they are asked
I am working on designing a Z80 computer and I would like to use a PS/2 ...
This is actually a fun little question to answer, because I get to go into how a CPU actually works, including the major difference between typical CISC and RISC architectures. In computing it is generally accepted that "moving" data is actually a copy operation, with the original remaining until overwritten; even in the bad old days of literal core memory, ...
I don’t think there’s a surefire way to detect the memory model being used at run-time, or even adjust code post-build in an object during linking. Libraries were provided in multiple variants, one for each supported memory model.
It is however possible to write code which will adjust to different memory models at build time, so a single assembly file can ...
Those two mnemonics opcodes are known to have the same timing / same inner mechanisms of mapping into HL.
It is obviously a bug in documentation from the link you give us. Those two pages you mention (86 and 87) were certainly edited based in the HL instruction, and someone forgot to edit that value to reflect the IY timing.
Also, do not focus much in ...