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12

Are there any similar Western examples of an instruction set with obviously cut corners Following on your example of having addition but not subtraction, the Intel 8080 has 8 bit addition and subtraction instructions laid out neatly as you can see in this table on rows 8x and 9x. The 8080 also has a 16 bit addition instruction DAD with opcode 0x09, but ...


9

The 6502, released in 1975, had a missing instruction when first released: it had a ROL (ROtate bits Left) instruction, but no corresponding ROR (ROtate bits Right) instruction. This was not an oversight on the designers' part, rather that the found a bug in the circuit for the ROR instruction during final testing. Rather than delay the release of their new ...


9

There are a lot of instructions on x86 that leave the flag(s) in an indeterminate state, which means the whole FLAGS register is also undefined. Most will have AF undefined, for example TEST The OF and CF flags are set to 0. The SF, ZF, and PF flags are set according to the result (see the “Operation” section above). The state of the AF flag is undefined....


5

Pascal compilers/runtimes typically do some (very often, optionally, enabled by a flag) run-time type checking. A very typical run-time check supported by most Pascal compilers is array bounds checking, because it is the most common type-related mismatch error in Pascal programs and bounds of actually used array indices are very hard to check at compile time ...


5

One example are the two undocumented 8085 flags that can be found by reverse-engineering the silicon (well, it's part of a register, not a complete register). They have uses for signed overflow in arithmetic operations and signed comparison. There are actually a few undocumented opcodes that make use of at least the K flag. They were put in deliberately (so ...


5

I'm finding this whole business kind of bizarre and hard to grok. So my question is basically "what's going on here?". It's a way to save on special case jump instructions. Or more general, to adapt certain instructions to work as needed due to prior executed ones. I guess today we would cover this on a programming level with a bunch of macro opcodes which ...


4

Some arithmetic operations in the Xerox Alto would leave registers in unpredictable states, as the cycle time was shorter than the total propagation time of the ALU: With a 137ns clock cycle time, the CP pushes the underlying hardware to its limits. As a result, some combinations of input sources requested by a microinstruction will not produce valid ...


4

As a matter of fact, the page you refer to, which was authored by me a long time ago, is somewhat incorrect, and bases its notation on a colloquial use of ω. In the original documentation ω is the name of the 1-bit signal generated by the arithmetic unit and consumed by the control unit. The UZA instruction takes the branch when ω=0. The 3-bit field in the ...


4

Compiling details pointed to in the comments by @secondperson and my own findings: It appears that the documentation is inaccurate. There are apparent typos and/or transcription errors. For example, the max. latency of the negation operation cannot be 25, as the operation involves negating a 40-bit 2's-complement value, which requires up to 40 clock cycles ...


3

Socialism is terrible - but there are other reasons for "cut corners" leading to missing instructions. For example, capitalism. In the minicomputer era it was reasonably common for there two be two variants of a machine: one without floating point and one with. You paid more $$$$ for the one with. I'm thinking specifically of the Honeywell 716 - but ...


1

And then there are data registers of various FPUs leaving one or more entries in unspecified state after an operation. Well known for example the AMD 9511 series where next to all higher FP functions like SIN or LOG working on a single argument leave at least two entries in undefined states (*1). *1 - Two operand functions always leave one entry undefined ...


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