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33 votes

Why does the Z80 have a half-carry bit?

The intermediate carry flag, or "adjust flag", or half-carry flag is used to facilitate binary-coded decimal (BCD) arithmetic, where each decimal digit of a number is represented as a nibble ...
Leo B.'s user avatar
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13 votes
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Behavior of the zero and negative/sign flags on classic instruction sets

Neither. In the 6502, the Z flag is set if there's an all-zero pattern on the internal data bus in the last instruction cycle and cleared if it isn't. This means specifically instructions as PLA or ...
Janka's user avatar
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12 votes
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How is FSTSW AX implemented on the 80286/80287?

Since this is about low level operation, let's start with the fact that the CPU/FPU does not provide an FSTSW AX instruction, only an FNSTSW AX. When encountering FSTSW AX, the assembler issues two ...
Raffzahn's user avatar
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11 votes
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Why does the Z80 have a half-carry bit?

Why does the Z80 have a half-carry bit? Because the ALU is only 4 bits wide. The Z80 needs to preserve the carry between bits 3 and 4. Why did the designers of this chip choose to preserve that ...
JeremyP's user avatar
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9 votes
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Does the 6502's TXS and TSX affect flags or not?

Does the 6502's TXS and TSX affect flags or not? TSX does affect N and Z TXS does not affect any flag In general all instructions moving data to one of the Registers (A, X, Y) do set N and Z ...
Raffzahn's user avatar
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8 votes

Which CPU was the first to clear the carry and overflow bits after performing logical operations?

TL;DR: I wonder if that observation is heavily biased by looking at today's all-influencing x86 architecture and its direct predecessors (x80). From my memory the described behaviour is only shown by ...
Raffzahn's user avatar
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8 votes

Behavior of the zero and negative/sign flags on classic instruction sets

While Wilson and Janka already explain the arithmetic and 6502 related (*1) implication, I somehow get the feeling this question is not about the 6502 Behavior of the zero and negative/sign flags on ...
Raffzahn's user avatar
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6 votes

Behavior of the zero and negative/sign flags on classic instruction sets

In the case you describe, the 6502 will set the Zero flag (in other words, the Z flag will be one if the operation left the accumulator equal to 0 mod 256). That's convenient, because usually a ...
Omar and Lorraine's user avatar
4 votes

Why 8086/8088 has OF in a high Flags byte?

I seem failing to explain this with 8080 compatibility, But that's exactly the point here - that way the flag byte is fully 8080 compatible. No matter what any software does to these bits. It will ...
Raffzahn's user avatar
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4 votes

What CPU architecture was first to implement 'inverted borrow' carry flag during subtractions?

The PDP-8, like a number of other architectures, doesn't have subtraction.  Thus, subtraction is necessarily done by negation followed by addition. The PDP-8 does have a carry bit (called the link bit)...
Erik Eidt's user avatar
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4 votes

Why does the Z80 have a half-carry bit?

The Intel 4004 and 4040 were 4-bit CPUs. In some ways, the 8008 and its successor, the 8080 behaved as if it were two 4004s glued together, although the 8008 architecture was not just two 4004s glued ...
Eric Towers's user avatar
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3 votes

Why does the Z80 have a half-carry bit?

The reason there needs to be a visible "half carry" bit is a combination of two factors. BCD support Interrupt handling. As other answers have pointed out the Z80 provided BCD support through an ...
Peter Green's user avatar
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