The intermediate carry flag, or "adjust flag", or half-carry flag is used to facilitate binary-coded decimal (BCD) arithmetic, where each decimal digit of a number is represented as a nibble (a group of 4 bits). The range of valid values for each nibble is 0 to 9 (0000 to 1001). If, after an arithmetic operation, the result contains a "non-...
Neither. In the 6502, the Z flag is set if there's an all-zero pattern on the internal data bus in the last instruction cycle and cleared if it isn't. This means specifically instructions as PLA or TAX affect the Z flag. On the 65C02, e.g. PLX does, too.
You can see this from the CMP, CPX, CPY, BIT instructions, which store nothing.
Same for the N flag, it'...
Does the 6502's TXS and TSX affect flags or not?
TSX does affect N and Z
TXS does not affect any flag
In general all instructions moving data to one of the Registers (A, X, Y) do set N and Z according to the data moved.
Excerpt of the instruction list from the 1976 data sheet on page 6:
Why does the Z80 have a half-carry bit?
Because the ALU is only 4 bits wide. The Z80 needs to preserve the carry between bits 3 and 4.
Why did the designers of this chip choose to preserve that value in the flags register?
Good question. You can't access the H bit directly except by saving the status register and then examining its contents, so there is ...
While Wilson and Janka already explain the arithmetic and 6502 related (*1) implication, I somehow get the feeling this question is not about the 6502
Behavior of the zero and negative/sign flags on classic instruction sets
but rather some generic, absolute meaning.
I'm very curious, cross-architecturally, how this has varied.
There is no variation, as ...
In the case you describe, the 6502 will set the Zero flag (in other words, the Z flag will be one if the operation left the accumulator equal to 0 mod 256). That's convenient, because usually a programmer is interested either in Z, to test for an actual zero condition, or in C, to test for a carry.
The Z80 works in the same way.
My understanding is that it'...
The Intel 4004 and 4040 were 4-bit CPUs. In some ways, the 8008 and its successor, the 8080 behaved as if it were two 4004s glued together, although the 8008 architecture was not just two 4004s glued together. For instance, the 8008 had an extensive carry prediction chunk attached to the ALU.
Adding either BCD or 4-bit values in the 4004 could result in ...
The reason there needs to be a visible "half carry" bit is a combination of two factors.
As other answers have pointed out the Z80 provided BCD support through an adjustment instruction run after the addition or subtraction operation (this constrasts with the 6502 that implemented it as a mode flag). This instruction needs ...