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57

An x86 CPU running in real mode is intended to be backwards-compatible with an 8086 or 8088, but there do end up being a number of differences, for example: newer CPUs run faster (in general); newer CPUs add new instructions (and, with the 386, new registers, since the 32-bit registers can be used in real mode); 286 and later CPUs add more address lines, ...


52

As far as I’m aware, the last FPU-less x86-compatible CPU which could still be considered general-purpose is the Vortex86SX, released in 2007 and still available now. This is a Pentium-class CPU, capable of running any Pentium code which doesn’t require an FPU. It is targeted at embedded applications, with up to 512 MiB of RAM, and includes a PCI bus, USB, ...


46

No, DOS won't use any additional CPU (*1) ever. (Though it might run faster due them new CPUs being faster) Quite the same way as DOS doesn't take advantage of the extended memory or additional instructions. DOS is a Single CPU Single User Single Task Single Program Real Mode 8086 operating system. Even through it got a few extensions over time to tap ...


43

The term x86 is shorthand for 80x86, which was used to refer to any member of the family 8086 (and also, incidently, 8088), 80186, 80286, etc. Things have since gotten a bit muddled by the fact that while an 80386 had a mode that was compatible with the old architecture, it also introduced some fundamentally new ways of doing things which were shared by the ...


42

I’m not sure the separate cache was “obviously better” back when the Intel designers were working on the 80486, at least, not to the designers in question. But “better” might not even have been much of a factor. The design history of the cache systems in Motorola and Intel CPUs is quite different, which can explain the different approaches used in the 68040 ...


37

It varies machine to machine; at the simplest end is the Neo Geo — its 68000 and Z80 have completely independent buses. You write one program for the 68000 and one for the Z80 and a single pipe of communication joins the two: post a byte to the Z80 and it'll trigger an NMI; the Z80 can read the command byte from a certain port and write a response to another,...


37

x is meant as wildcard, so this represents all CPUs able to run 8086 compatible code.


32

What reasons would CPU designers have for choosing these different approaches? It depends on what the designers intended to mark a valid bus cycle, which is the 'leading' signal for decoding. In a more general way, it's the design view of the bus. Common ways (*1) are: The 8080 way - Marking a cycle by a one of several (*2) dedicated signals marking the ...


27

The 8085 is effectively the same as the 8080 microprocessor. The 8080 has a flat 16-bit address space and no segment registers. So yes, the 8085 uses real memory addresses without any translation.


27

No. There is no mechanism for any privilege levels or protection in 8086. As a consequence, there is nothing special about OS code, and thus user applications are allowed to do everything, including reading and writing to any physical memory address, directly access any I/O port, and enable/disable interrupts at will. Protected mode was introduced in 80286....


24

how do CPU cards work on the Apple II if there's no way to take the bus over? That's what /DMA (pin 22) is good for. It halts the CPU and tristates the bus. Now any card can take over. Unlike its daddy, the 6800 (and many other CPUs as well), the 6502 can be halted in at any clock state by pulling /RDY. It will extend the actual cycle (*1). This doesn't ...


23

From your source code, it looks like you're expecting to be able to find individual songs as standalone assembly listings for a 'master' CPU (such as your 8086) that you can execute to play a song on a sound chip. Outside of very small examples, that's not a very useful way to use a sound chip, since unless the song code is designed like a coroutine, you won'...


21

Full, hardware-assisted virtualisation, with the intention of supporting hypervisors running operating systems without requiring para-virtualisation, was added to micro-processors relatively recently. (Many RISC-style architectures were virtualisable following Popek and Goldberg’s criteria, and were used in high-end partitionable systems, but with external ...


21

Stephens Answer already carries most implications, so this is merely an add-on. First to keep in mind is that the 68k was way more in need of a cache than x86 CPUs, as its memory access was in line with execution, while the x86 prefetch buffer used 'free' cycles to read ahead, thus utilizing the memory much better than the 68k could do (*1). Next, it ...


16

All Intel x86 CPUs since the 80486 line have included floating point instructions, i.e. everything from the Pentium* onward. So the last Intel processor to lack an on-board floating-point unit (FPU) was the 80486SX (and the embedded 80486GX). Other manufacturers, who made 486-compatible processors, continued making non-FPU chips, aiming for the budget ...


15

I'm actually not aware of any major 8080 test suites; everything I've ever found has been for the Z80 rather than its parent. That aside, I'd heavily suggest you don't discard the CP/M solutions you've found as they're usually pretty trivial to set up as test cases without any of the main substance of a CP/M environment. For example, to run the CP/M ...


14

Simply Yes. A basic 8080/85 (or Z80) does just output the 16 bit address generated by an instruction. There is no inherent translation, Segmentation or whatsoever.


13

If by IBM DOS you mean IBM PC DOS, which was a rebrand/derivate of MS-DOS, then the answer is no - DOS will only ever support a single core. HyperThreading and multiple cores is simply not supported by DOS. Making DOS use multiple cores would be a major operation. Firstly DOS would have to support multitasking. It could not be task switching or cooperative ...


11

"A Retrospective on MIPS: A Microprocessor Architecture", authored by those that designed MIPS from the beginning, states: The absence of hardware interlocks (to delay an instruction if one of the operands wasn’t ready) was a tradeoff... [...] The team wanted to pick a name for the project that emphasized performance. About nine months earlier, ...


11

I'm curious how these chips actually worked. Similarities [...] They are so similar, that Zip Technologies even won the case against Rocket-Chips manufacturer Bits & Pieces. Just, the manual doesn't tell a lot about the inner workings. Only that it's a "technological marvel" with the equivalent of "350 integrated logic chips" and "hundrets of tiny gold ...


10

There are two basic techniques: shared memory and dedicated communication ports. Shared memory simply allows both processors to access the same memory bus. There are some issues, as the bus has to be shared and one CPU has to get priority so code must be designed to take unpredictable extra delays into account. The Megadrive is a good example of that, with ...


10

Where could I find a list of all of the microchips released by Intel, including microprocessors, Rams, roms, storage devices. Etc. Oh, that's a simple one: Get the Databooks Intel, like any other manufacturer, has a good history of publishing big volumes of databooks and even more datasheets. At least all basic chips that ever made it into production (and ...


10

To answer the second part of the question, yes, any program could do what the OS could do. Some of the useful reasons included: Directly access hardware, especially to provide support for third-party expansion cards. Directly access graphics memory, to draw graphics. Overwrite system calls, to alter or extend the functionality of the OS. Certain TSR ...


10

For example, could Sega Genesis play heavier games if its video chip were replaced with a second Motorotola 68000 (8 Mhz) in the program of which video algorithms would be implemented? No, it would be slower - much slower. The Yamaha YM7101 VDP can display 80 32x32 pixel sprites (20 per scanline), over 2 tile maps which can be freely scrolled vertically ...


9

Yes; it's called Chen-Ho encoding Theodore M. Hertz of Rockwell filed for a patent on a similar encoding in 1969. The patent was granted in 1971. Independently in 1971, IBM researchers Tien Chi Chen and Irving Tze Ho worked on encoding two decimal digits in 7 bits. The company filed for a patent in 1973, citing Hertz' patent as prior art, which was ...


9

In modern usage it also means software which only uses the 32-bit architecture of the earlier 80x86 processors, to distinguish it from 64-bit applications. Microsoft uses it that way on 64-bit versions of Windows, which have two separate directories called "Program Files" and "Program Files (x86)." The 32-bit applications will run on 64-bit hardware, but ...


9

Segment registers can be changed, thus allowing access to full address space. In addition to doing this ad hoc, there are different ways to model this, called memory models: small: code and data both reside in one segment, all code and data pointers are 16bit medium: single data segment, multiple code segments (code pointers 32bit) compact: single code ...


8

The MIPS architecture was introduced in 1981 Are you sure? To my information the first MIPS implementation was of 1985 with the R2000. Of course, the project did start before (in 1981), but so did others. It is my understanding that VLIW architectures which also have an exposed pipeline, came later. Is that true? As far as I can tell, yes. Was MIPS ...


8

In the original ARM instruction set there are no dedicated shift and roll instructions; instead the second operand of each instruction always passes through the barrel shifter, so shifts and rolls are always applied as prefixes to other operations. You can make the instruction a simple MOV to get the same result as a traditional shift or rotate operation. ...


8

As you surmise, one way of dividing up graphic image generation is into two parts: building a bitmap in memory (with or without hardware assistance) and then converting the bitmap into a video signal. And that is how modern graphics cards do this. Some older systems also did this, but as well there were three other common methods of dividing up the work. ...


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