I suspect your teacher was referring to the FDIV Pentium bug, which led to a large outcry in the media at the time and for which Intel issued a recall.
This bug caused floating-point division to return incorrect results in some cases. It didn’t affect only FDIV, some related instructions were affected: the other division and remainder instructions, and FPTAN ...
Fast multiplier circuits as used today take enormous amounts of logic, far beyond what would have been cost-effective (or perhaps even possible) in the mid-70s for an inexpensive microprocessor. Even slow multiplier circuits (as would appear later on chips like the 6809, 68000 or 8086) use a fair bit of logic and would have very considerably added to the ...
An x86 CPU running in real mode is intended to be backwards-compatible with an 8086 or 8088, but there do end up being a number of differences, for example:
newer CPUs run faster (in general);
newer CPUs add new instructions (and, with the 386, new registers, since the 32-bit registers can be used in real mode);
286 and later CPUs add more address lines, ...
You don't need it
Multiplying two arbitrary bytes together has limited practical value. (If you want to multiply by a constant you can hardcode the optimal sequence of instructions to do so.)
Obviously it would be nice to have but the expense isn't worth it.
In an arcade game... you basically never need to multiply a thing. To draw lines or circles, you can ...
As far as I’m aware, the last FPU-less x86-compatible CPU which could still be considered general-purpose is the Vortex86SX, released in 2007 and still available now. This is a Pentium-class CPU, capable of running any Pentium code which doesn’t require an FPU. It is targeted at embedded applications, with up to 512 MiB of RAM, and includes a PCI bus, USB, ...
The term x86 is shorthand for 80x86, which was used to refer to any member of the family 8086 (and also, incidently, 8088), 80186, 80286, etc. Things have since gotten a bit muddled by the fact that while an 80386 had a mode that was compatible with the old architecture, it also introduced some fundamentally new ways of doing things which were shared by the ...
Manufacturing simple processors on newer semiconductor processes is done. But not quite to that extreme.
Let's consider your proposed 8086 done in a 14 nm process. Let's say we do it in CMOS, and maybe even throw in a few extra features, and it takes 100,000 transistors. The die would be very tiny, so unbelievably tiny. You could fit three thousand of ...
No, DOS won't use any additional CPU (*1) ever.
(Though it might run faster due them new CPUs being faster)
Quite the same way as DOS doesn't take advantage of the extended memory or additional instructions.
DOS is a
Even through it got a few extensions over time to tap a ...
It appears that A0 through A6 operate correctly, but A7 though A9 (I've not tested the rest of the upper bits) are only active on the clock edge.
Doesn't that exactly look like refresh cycles? :))
Basic Z80 bus behaviour, here especially the M1 cycle:
Z80 timing is structured in Machine cycles (M-states).
A machine cycle consists of several Clock cycles (T-...
I’m not sure the separate cache was “obviously better” back when the Intel designers were working on the 80486, at least, not to the designers in question.
But “better” might not even have been much of a factor. The design history of the cache systems in Motorola and Intel CPUs is quite different, which can explain the different approaches used in the 68040 ...
Older CPUs have been shrunk to smaller sizes but not in the same way as modern design, simply as there is no gain in doing so.
Does the industry continue to produce outdated architecture CPUs with leading-edge process?
No. Designs shrink, but there is no sense in using leading-edge sizes for such 'small' designs.
However, is there any CPU ...
It varies machine to machine; at the simplest end is the Neo Geo — its 68000 and Z80 have completely independent buses. You write one program for the 68000 and one for the Z80 and a single pipe of communication joins the two: post a byte to the Z80 and it'll trigger an NMI; the Z80 can read the command byte from a certain port and write a response to another,...
In short, to better support interrupts, because interrupts were
arguably broken (or at least very limited in usability) on the 8008.
The direct answer to the question of why you'd move the stack off-die is
"space": they needed a bigger stack and dedicating a lot of die space for a
larger stack on the 8080 was basically a non-starter. But the ...
Besides the matter of semantics and personal taste, there’s a much more practical reason: some instructions sets claim to be copyrighted, as the Wikipedia Z80 article states:
Because Intel claimed a copyright on their assembly mnemonics, a new assembly syntax had to be developed for the Z80. This time a more systematic approach was used.
So, I think the ...
What reasons would CPU designers have for choosing these different approaches?
It depends on what the designers intended to mark a valid bus cycle, which is the 'leading' signal for decoding. In a more general way, it's the design view of the bus.
Common ways (*1) are:
The 8080 way - Marking a cycle by a one of several (*2) dedicated signals marking the ...
Worshipping at the altar of color clock
Back in that day, everything was built around the NTSC color clock frequency of 3.579545 MHz. Everything from the Atari VCS to the C64 made ample use of it, because some iteration of your product would inevitably need to talk to a commodity color NTSC display operating at that frequency.
This will come up; so FYI ...
The main issue with the 80186 isn’t with the CPU core itself, but with its integrated peripherals: they aren’t compatible with those used in the IBM PC, and they aren’t integrated in the same way either.
The IBM PC uses an 8237 DMA controller at offset 0x00 in the I/O address space, an 8259 PIC at offset 0x20, and an 8253 PIT at offset 0x40. The 80186’s ...
The extra pins were forward-planning, on both Socket 2 and Socket 3. Most of the extra pins are used for power (Vcc) and ground (Vss), which is useful to provide more power to a CPU. The other pins are keys, a new INIT pin (F19), and signals used for enabling and controlling the write-back L1 cache. (See the socket 3 specifications in the 486 family ...
No, they cannot.
They share both the data and the address bus of the C128, so they can only run exclusively at any one point in time.
The address bus is apparently directly connected, the data bus of the Z80 through a set of latches to the data bus of the rest of the system.
In CP/M mode, the 8502 is handling keyboard, screen and printer and serial ...
Because "move" is the typical necessary function
It isn't always this way, of course, but especially with earlier CPUs, there were limited destinations for data from a particular operation - e.g., arithmetic results could only be in certain registers. Or in the other direction, certain functions could only operate on a few locations, typically registers or ...
No. There is no mechanism for any privilege levels or protection in 8086. As a consequence, there is nothing special about OS code, and thus user applications are allowed to do everything, including reading and writing to any physical memory address, directly access any I/O port, and enable/disable interrupts at will.
Protected mode was introduced in 80286....
Stephen Kitt has already provided a good answer regarding the FDIV bug. I'll fill in some details about Intel employing logicians:
Because of this bug, Intel had to replace a lot of processors, which was very expensive. Not wanting to repeat this, they hired a number of computer scientists with background in formal logic to prove the correctness of ...
Throwing some things out there that might fit the bill:
6502: AllSuiteA which assembles into a single binary and exits, leaving a failure or success code in memory;
6502 and 65C02: Klaus Dormann's test suite also compiles into a single binary per target CPU, but loops in place if it finds an error rather than exiting;
6502: Wolfgang Lorenz's tests cover the ...
Classic RISC CPUs like ARM ... instructions execute in one cycle ...
This assumption is not correct.
The ARM-2 CPU (VL86C010, one of the first ARM CPUs) took:
Only one cycle for most operations (as you expected it)
Typically two cycles if a jump/branch was done
Up to 4 cycles for shift/rotate operations
Up to 16 cycles for multiply operations
Up to 17 (or ...
For many kinds of parts, there's a substantial gap between specified maximum/minimum timings and typical timings. The 8088 specification requires that the clock be high for a minimum of 69 ns every cycle and low for a minimum of 118 ns. Dividing a 14.3818 Mhz clock by three yields a high time of 69.5 ns and a low time of 139.1 ns, satisfying both ...
Here’s the list of main technologies used:
4004: 10µm PMOS;
4040: 10µm PMOS;
8008: 10µm PMOS;
8080: 6µm NMOS (faster than PMOS, and TTL-compatible);
8085: 3.2µm NMOS, then HMOS (“H” variants);
8086: 3.2µm NMOS, then HMOS (in three iterations) and CHMOS (static variants);
80186: 3.2µm HMOS and CHMOS;
80286: 1.5µm HMOS (also CMOS, at least from other ...
Let's start with a basic misconception here:
it said that it uses a CP1600 that is based off a PDP-11.
No. It isn't. It is a far descendant of the PDP-8 - or more exactly, the PDP-X. The PDP-X was a skunkworks project lead by Edson de Castro to improve manufacturing density (*1) and move DEC's development away from their 6 bit line (PDP-8/9/10/...) toward ...