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56

An x86 CPU running in real mode is intended to be backwards-compatible with an 8086 or 8088, but there do end up being a number of differences, for example: newer CPUs run faster (in general); newer CPUs add new instructions (and, with the 386, new registers, since the 32-bit registers can be used in real mode); 286 and later CPUs add more address lines, ...


52

As far as I’m aware, the last FPU-less x86-compatible CPU which could still be considered general-purpose is the Vortex86SX, released in 2007 and still available now. This is a Pentium-class CPU, capable of running any Pentium code which doesn’t require an FPU. It is targeted at embedded applications, with up to 512 MiB of RAM, and includes a PCI bus, USB, ...


47

The term x86 is shorthand for 80x86, which was used to refer to any member of the family 8086 (and also, incidently, 8088), 80186, 80286, etc. Things have since gotten a bit muddled by the fact that while an 80386 had a mode that was compatible with the old architecture, it also introduced some fundamentally new ways of doing things which were shared by the ...


45

No, DOS won't use any additional CPU (*1) ever. (Though it might run faster due them new CPUs being faster) Quite the same way as DOS doesn't take advantage of the extended memory or additional instructions. DOS is a Single CPU Single User Single Task Single Program Real Mode 8086 operating system. Even through it got a few extensions over time to tap ...


42

I’m not sure the separate cache was “obviously better” back when the Intel designers were working on the 80486, at least, not to the designers in question. But “better” might not even have been much of a factor. The design history of the cache systems in Motorola and Intel CPUs is quite different, which can explain the different approaches used in the 68040 ...


41

It appears that A0 through A6 operate correctly, but A7 though A9 (I've not tested the rest of the upper bits) are only active on the clock edge. Doesn't that exactly look like refresh cycles? :)) Basic Z80 bus behaviour, here especially the M1 cycle: Z80 timing is structured in Machine cycles (M-states). A machine cycle consists of several Clock cycles (...


38

x is meant as wildcard, so this represents all CPUs able to run 8086 compatible code.


37

It varies machine to machine; at the simplest end is the Neo Geo — its 68000 and Z80 have completely independent buses. You write one program for the 68000 and one for the Z80 and a single pipe of communication joins the two: post a byte to the Z80 and it'll trigger an NMI; the Z80 can read the command byte from a certain port and write a response to another,...


36

Besides the matter of semantics and personal taste, there’s a much more practical reason: some instructions sets claim to be copyrighted, as the Wikipedia Z80 article states: Because Intel claimed a copyright on their assembly mnemonics, a new assembly syntax had to be developed for the Z80. This time a more systematic approach was used. So, I think the ...


32

What reasons would CPU designers have for choosing these different approaches? It depends on what the designers intended to mark a valid bus cycle, which is the 'leading' signal for decoding. In a more general way, it's the design view of the bus. Common ways (*1) are: The 8080 way - Marking a cycle by a one of several (*2) dedicated signals marking the ...


31

Worshipping at the altar of color clock Back in that day, everything was built around the NTSC color clock frequency of 3.579545 MHz. Everything from the Atari VCS to the C64 made ample use of it, because some iteration of your product would inevitably need to talk to a commodity color NTSC display operating at that frequency. This will come up; so FYI ...


29

No, they cannot. They share both the data and the address bus of the C128, so they can only run exclusively at any one point in time. The address bus is apparently directly connected, the data bus of the Z80 through a set of latches to the data bus of the rest of the system. In CP/M mode, the 8502 is handling keyboard, screen and printer and serial ...


27

The 8085 is effectively the same as the 8080 microprocessor. The 8080 has a flat 16-bit address space and no segment registers. So yes, the 8085 uses real memory addresses without any translation.


27

No. There is no mechanism for any privilege levels or protection in 8086. As a consequence, there is nothing special about OS code, and thus user applications are allowed to do everything, including reading and writing to any physical memory address, directly access any I/O port, and enable/disable interrupts at will. Protected mode was introduced in 80286....


27

Because "move" is the typical necessary function It isn't always this way, of course, but especially with earlier CPUs, there were limited destinations for data from a particular operation - e.g., arithmetic results could only be in certain registers. Or in the other direction, certain functions could only operate on a few locations, typically registers or ...


26

For many kinds of parts, there's a substantial gap between specified maximum/minimum timings and typical timings. The 8088 specification requires that the clock be high for a minimum of 69 ns every cycle and low for a minimum of 118 ns. Dividing a 14.3818 Mhz clock by three yields a high time of 69.5 ns and a low time of 139.1 ns, satisfying both ...


24

how do CPU cards work on the Apple II if there's no way to take the bus over? That's what /DMA (pin 22) is good for. It halts the CPU and tristates the bus. Now any card can take over. Unlike its daddy, the 6800 (and many other CPUs as well), the 6502 can be halted in at any clock state by pulling /RDY. It will extend the actual cycle (*1). This doesn't ...


23

From your source code, it looks like you're expecting to be able to find individual songs as standalone assembly listings for a 'master' CPU (such as your 8086) that you can execute to play a song on a sound chip. Outside of very small examples, that's not a very useful way to use a sound chip, since unless the song code is designed like a coroutine, you won'...


22

The change in the MOS designator from 65xx to 85xx was due to the process change - original 65xx were NMOS process, while later 85xx changed to the new HMOS process. This allowed for better densities and lower power dissipation. A positive benefit being that the 85xx used less power even at higher speeds, with obvious benefits for cooling, PSU budget, and ...


22

Were there any 8-bit CPUs with 24-bit addressing? Not many. Most prominent and best fitting examples would be WDC 65816 of 1983 Hitachi 64180 of 1985 / Zilog Z180 of 1985 (only 19/20 bit) eZ80 of 1998 Then there 8/16/32 bit hybrids - able to run 8 bit code and available with external 8 bit data bus, but as well with 16/32 bit code (extensions): Zilog ...


21

Full, hardware-assisted virtualisation, with the intention of supporting hypervisors running operating systems without requiring para-virtualisation, was added to micro-processors relatively recently. (Many RISC-style architectures were virtualisable following Popek and Goldberg’s criteria, and were used in high-end partitionable systems, but with external ...


21

Stephens Answer already carries most implications, so this is merely an add-on. First to keep in mind is that the 68k was way more in need of a cache than x86 CPUs, as its memory access was in line with execution, while the x86 prefetch buffer used 'free' cycles to read ahead, thus utilizing the memory much better than the 68k could do (*1). Next, it ...


20

Classic RISC CPUs like ARM ... instructions execute in one cycle ... This assumption is not correct. The ARM-2 CPU (VL86C010, one of the first ARM CPUs) took: Only one cycle for most operations (as you expected it) Typically two cycles if a jump/branch was done Up to 4 cycles for shift/rotate operations Up to 16 cycles for multiply operations Up to 17 (or ...


18

Quartz used in colour TVs such as 3.579545MHz or 14.31818MHz used to be much cheaper than other frequencies. It was important for home computers and game consoles (8/16 bits), which used the same quartz for video and the CPU, keeping everything synchronous. It was far less siginificant for rather expensive computers such as IBM PC which didn't need to ...


17

TL;DR It's all about getting systematic, easy to memorise mnemonics, which may reflect some underlaying structure, but most important ease practical use. Exact language is not always a handy one - except you're asking a lawyer :) So why call the instruction "move"? Oh, the age old copy-vs-move question. A beloved friend :) There are many different, ...


16

I'm actually not aware of any major 8080 test suites; everything I've ever found has been for the Z80 rather than its parent. That aside, I'd heavily suggest you don't discard the CP/M solutions you've found as they're usually pretty trivial to set up as test cases without any of the main substance of a CP/M environment. For example, to run the CP/M ...


16

All Intel x86 CPUs since the 80486 line have included floating point instructions, i.e. everything from the Pentium* onward. So the last Intel processor to lack an on-board floating-point unit (FPU) was the 80486SX (and the embedded 80486GX). Other manufacturers, who made 486-compatible processors, continued making non-FPU chips, aiming for the budget ...


14

Simply Yes. A basic 8080/85 (or Z80) does just output the 16 bit address generated by an instruction. There is no inherent translation, Segmentation or whatsoever.


13

If by IBM DOS you mean IBM PC DOS, which was a rebrand/derivate of MS-DOS, then the answer is no - DOS will only ever support a single core. HyperThreading and multiple cores is simply not supported by DOS. Making DOS use multiple cores would be a major operation. Firstly DOS would have to support multitasking. It could not be task switching or cooperative ...


12

Support for byte writes throughout a memory system is expensive. Among other things, if one wishes to use error-corrected memory that can correct single-bit errors, a memory that can be written in independent 8-bit chunks byte-writable memory will require four extra bits per octet, or 16 bits per 32-bit word. A memory that is limited to writing 16-bit ...


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