44 votes
Accepted

Using DRAM as a camera sensor?

That sounds a lot like the Cromemco Cyclops. Released in 1975, it used a modified1 MOS 1kbit DRAM2 to capture a 32×32 black and white or greyscale image. The memory cells were initially set to all ...
Alex Hajnal's user avatar
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32 votes
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What is DRAM refresh and why is the weird Apple II video memory layout affected by it?

Summary Each DRAM chip has multiple "rows" of memory, and each row needs to be accessed in a certain way (not necessarily via a read or write) on a regular basis in order to avoid the memory ...
cjs's user avatar
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26 votes

What is DRAM refresh and why is the weird Apple II video memory layout affected by it?

DRAM requires that each row of the memory is read and re-written regularly, at least every few milliseconds for the devices available at the time the Apple II was designed. This contrasts with the ...
Chromatix's user avatar
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22 votes
Accepted

Was any DRAM ever slower than 2 MHz?

From the 1975 Intel Data Catalog entry for the 1103: one sees that a write or read/write cycle is specified as a minimum of 580 nsec. This corresponds to a speed of 1.724 MHz.
Jon Custer's user avatar
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15 votes
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What process node were 4k and 16k DRAMs first made at?

Intel manufactured its 1-kilobit 1103 RAM on an 8 μm P-MOS process. Through most of the 1970s, DRAM was made from NMOS. The first successful CMOS memory was the Hitachi HM6147 SRAM, a 4-kilobit chip ...
Davislor's user avatar
  • 8,686
14 votes

When did CPUs start using page mode DRAM?

DRAM access in general and page mode (*1) in particular are not CPU features, but depend on the DRAM controller. No matter if build by discrete components (like mulitiplexers and counters) or ...
Raffzahn's user avatar
  • 223k
13 votes

Using DRAM as a camera sensor?

Alex Hajnal's answer pretty well describes what I believe is the first and eventually only commercial available camera that directly used RAM chips, the Cyclops (*1). It started out as a hobby level ...
Raffzahn's user avatar
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13 votes
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How did the ZX80 RAM pack use DRAM?

But as I understand it, the then current 16kbit RAM chips actually required three different voltages: -5, +5, +12. Right, and the 'missing' voltages (-5V,+12V) get generated from the +9V source via a ...
Raffzahn's user avatar
  • 223k
12 votes
Accepted

What sort of RAM chips did the Commodore 64 use in 1994?

The highest capacity DRAM to ever be used for the Commodore 64 motherboard was 256Kbit. By the early 1990s, 1Mbit DRAM was commonplace, but used in a 256Kbx4 would require the C64 to have 256KB of ...
Brian H's user avatar
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11 votes
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Cost of dynamic versus static RAM in the early days

I did find some prices in BYTE: November 1975, page 91 2107 4Kx1 Dynamic: $19.95 (0.49 cents/byte) 2111 256x4 Static: -- not listed 1101 256x1 Static: $2.25 (0.89 cents/byte) April ...
Eugene Styer's user avatar
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11 votes
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When did CPUs start using page mode DRAM?

Outside of the world of microprocessors, there were plenty of CPUs that did this. Up until some point in the mid 80s, TTL-based multichip CPUs were generally faster than microprocessors and therefore ...
Jules's user avatar
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11 votes
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Why doesn't the Acorn Electron use fast page mode?

This diagram comes from page 7 of the Electron service manual: As you can see, both CPU and VDU accesses involve a single RAS and two CASs. It is therefore using page mode.
Tommy's user avatar
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10 votes
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How fast did the ARM-1 access memory?

[Partial answer about how it supports FPM RAM - I still need to look up the manual for timing details] Support for (Fast) Page Mode RAM (*1) The CPU supports N and S-cycles (ARM lingo) or Non-...
Raffzahn's user avatar
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10 votes
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How does DRAM refresh work in the Leningrad?

There's just one thing though: the Z80 doesn't flip the highest bit of the R register, True and so R only iterates across 32k. Not really, it doesn't access 32 Ki but 128 rows. So how does the ...
Raffzahn's user avatar
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10 votes
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Did any 8-bit computers use 16kx4 RAM chips?

Quite a lot - well, not many different, as those chips came at a time when computers with only 16 KiB as base memory - and that's where 4416 would have been a cost saver - were already on the way out. ...
Raffzahn's user avatar
  • 223k
9 votes

Why were ZIP DRAM packages ever considered if PLCC/SOJ sockets were available?

Most important is that ZIP offered higher density while still being thru-hole, thus compatible with existing manufacturing technology. Sockets are generally avoided as sockets are a cost factor. They ...
Raffzahn's user avatar
  • 223k
8 votes

Using DRAM as a camera sensor?

We tried it in the lab, circa 1984. I worked with a hardware team and somewhere they'd read an article, the gist of which was something like: write all 1s to the DRAM ensure you don't have any ...
jonathanjo's user avatar
8 votes

Cost of dynamic versus static RAM in the early days

My firm designed microcomputer boards in the late 1970s to early 1980s, and we often had discussions about whether a particular design was going to use static or dynamic RAM. When you say "static RAM,...
jonathanjo's user avatar
8 votes

What is DRAM refresh and why is the weird Apple II video memory layout affected by it?

What exactly is DRAM refresh? Is it simply making sure a memory cell is accessed which gives it an electrical charge to keep it alive, or is it more like a 'read and re-write'? Both. DRAM stores it'...
Raffzahn's user avatar
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7 votes
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What was the DRAM refresh interval on early microcomputers?

Was 4 ms the typical figure for standard DRAM chips? Only starting with 128kbit and 256kbit chips. Many earlier chips (16kbit, 32kbit, 64kbit) and some 128kbit chips were documented as requiring a 2 ...
Stephen Kitt's user avatar
7 votes

How does DRAM refresh work in the Leningrad?

From the schematics, I can see this uses a single RAM bank, opposed to the original Sinclair machine, which uses two separate RAM banks. That means that the entire RAM address space must be shared ...
mcleod_ideafix's user avatar
7 votes
Accepted

Why do Early DRAMs (e.g. 4116) have a negative Column Address Set-up Time?

The 4116 was likely designed during in an era (or semiconductor technology node) when self-timed-delay pre-charge-evaluate NMOS logic cascades were common. (e.g. rather than synchronously or edge ...
hotpaw2's user avatar
  • 8,183
7 votes

Using DRAM as a camera sensor?

Sorry to come late to this party. One thing to note is that, in order to use the DRAM in the way that the Cromemco Cyclops does, it must be a design with a non-destructive read. The 4008 parts (both ...
William Sudbrink's user avatar
7 votes
Accepted

How does the VIC-II/CPU memory access work on the C64?

First, it is helpful to recognize that the C64's VIC-II chip is more the "master" over the C64 system (address/data/memory) bus than the 6510 CPU. How is this so? The VIC-II doesn't just ...
Brian H's user avatar
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7 votes
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Did the Vic-20 save money using static RAM?

Interfacing static RAM and ROM to an 6502-type processor is "nearly free". You just wire address and data lines directly, the address decoding circuit is simple. Nothing else is needed. On ...
Michael Karcher's user avatar
6 votes

When did CPUs start using page mode DRAM?

A number of British 8-bit home computers built around Ferranti ULAs used page mode in some way. The timings for DRAM are tricky. If you look at the timings they aren't nice multiples. Even with, say, ...
Tom Hawtin - tackline's user avatar
6 votes

Were there low-end eighties computers that used dual-ported video RAM?

Well, depends on the definition of dual port. After all, all 9918ff based machines can as well be classified as dual ported. Similar PC graphic cards, like VGA. Beside that, the most most important ...
Raffzahn's user avatar
  • 223k
6 votes

How does POST memory test work on a relatively modern (2000s) PC? Does it still test every single byte like on older ones?

Because dynamic RAM's switch-on contents is random, the memory of a computer needs to be brought to a defined state anyways. The clearing (and clear-check afterwards) is and was also the method of ...
tofro's user avatar
  • 35k
6 votes

TMS9918 - why have separate data-in and data-out?

Let's see the datasheet for 9918 first and see how the VDP to VRAM write sequence works. Before the write cycle, the VRAM chips were all held in the READ mode (R/~W signal is held high by VDP). This ...
user3528438's user avatar
  • 1,395
6 votes

Why doesn't the Acorn Electron use fast page mode?

Is there some technical reason this would not work, or am I misunderstanding the situation? Both. First of all, it already uses PM when running at 1 MHz. Second it's basically a 2 MHz system with the ...
Raffzahn's user avatar
  • 223k

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