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43

That sounds a lot like the Cromemco Cyclops. Released in 1975, it used a modified1 MOS 1kbit DRAM2 to capture a 32×32 black and white or greyscale image. The memory cells were initially set to all 1s. As they were exposed to light they would progressively switch to 0s; the more light hitting a cell, the faster the transition4. By making multiple read ...


24

DRAM requires that each row of the memory is read and re-written regularly, every few tens of milliseconds at least. This is made much easier by the DRAM chip having a row buffer which is filled with the contents of the row every time the /RAS strobe is triggered, and written back when it is released. So it is only necessary for the computer to arrange for ...


20

Summary Each DRAM chip has multiple "rows" of memory, and each row needs to be accessed in a certain way (not necessarily via a read or write) on a regular basis in order to avoid the memory "fading away." (Basically, this access recharges the capacitors from which the DRAM row is made.) The Apple II uses two tricks to do this refresh. ...


14

Intel manufactured its 1-kilobit 1103 RAM on an 8 μm P-MOS process. Through most of the 1970s, DRAM was made from NMOS. The first successful CMOS memory was the Hitachi HM6147 SRAM, a 4-kilobit chip which used a 3 μm CMOS process. This was not the first 4-kb chip on the market (it was preceded by, among others, the Intel 2114 SRAM), but it’s more comparable ...


13

Alex Hajnal's answer pretty well describes what I believe is the first and eventually only commercial available camera that directly used RAM chips, the Cyclops (*1). It started out as a hobby level project, about the same time chip manufacturers did build the first dedicated CCD camera elements. CCDs were like the super hype of the 70s - at least to ...


12

The highest capacity DRAM to ever be used for the Commodore 64 motherboard was 256Kbit. By the early 1990s, 1Mbit DRAM was commonplace, but used in a 256Kbx4 would require the C64 to have 256KB of main memory. It was almost certainly cheaper to continue to source the 256Kbit RAMs than to either upgrade the C64 to support 256KB of RAM near its end-of-life, or ...


11

I did find some prices in BYTE: November 1975, page 91 2107 4Kx1 Dynamic: $19.95 (0.49 cents/byte) 2111 256x4 Static: -- not listed 1101 256x1 Static: $2.25 (0.89 cents/byte) April 1976, page 89 2107 4Kx1 Dynamic: $19.95 (0.49 cents/byte) 2111 256x4 Static: $7.95 (0.77 cents/byte) 1101 256x1 Static: $2.25 (0.89 cents/byte) Byte ...


9

But as I understand it, the then current 16kbit RAM chips actually required three different voltages: -5, +5, +12. Right, and the 'missing' voltages (-5V,+12V) get generated from the +9V source via a discrete DC-DC converter - that's all the little pieces on the second board. The difference between the RAM-Packs for ZX80/81 is all in the colour :) In fact, ...


9

There's just one thing though: the Z80 doesn't flip the highest bit of the R register, True and so R only iterates across 32k. Not really, it doesn't access 32 Ki but 128 rows. So how does the Leningrad refresh the entire DRAM? Well, like any other machine using 4164 RAMs - by refreshing all 128 rows. It is important to separate address ...


8

What exactly is DRAM refresh? Is it simply making sure a memory cell is accessed which gives it an electrical charge to keep it alive, or is it more like a 'read and re-write'? Both. DRAM stores it's information in the charge of a capacitor(*1). Capacitors leak. Chip capacitors leak faster than discrete ones,and small ones even faster (*2)- DRAM chips have ...


8

We tried it in the lab, circa 1984. I worked with a hardware team and somewhere they'd read an article, the gist of which was something like: write all 1s to the DRAM ensure you don't have any hardware dynamic RAM refresh going on expose it for a given period read the decayed bits back I believe that we ended up having to write 1s or 0s depending on the ...


7

My firm designed microcomputer boards in the late 1970s to early 1980s, and we often had discussions about whether a particular design was going to use static or dynamic RAM. When you say "static RAM, because it's quite a bit easier to get to work", you also need to remember that the refresh circuits cost design time, chips, and board space. (No surface-...


7

Sorry to come late to this party. One thing to note is that, in order to use the DRAM in the way that the Cromemco Cyclops does, it must be a design with a non-destructive read. The 4008 parts (both AMI and Mostek) are three transistor per cell DRAM designs with non-destructive reads. One other piece of information that I can provide is that, on an S-100 ...


7

From the schematics, I can see this uses a single RAM bank, opposed to the original Sinclair machine, which uses two separate RAM banks. That means that the entire RAM address space must be shared between the video circuit and the CPU, while the original Sinclair machine only shared 16KB of RAM. Now, it happens that DRAMs are not only refreshed using RAS ...


5

My recollection was that 4 kbit and 16 kbit DRAMS were being manufactured in volume around roughly circa same time frame as when 8 micron NMOS fabrication was common for other stuff. This web site seems to support that hypothesis: https://en.wikichip.org/wiki/8_µm_lithography_process


5

Was 4 ms the typical figure for standard DRAM chips? Only starting with 128kbit and 256kbit chips. Many earlier chips (16kbit, 32kbit, 64kbit) and some 128kbit chips were documented as requiring a 2 ms refresh cycle; see these tables for details: 4116, 4132, 4164, 41128, 41256. The fact that many computers used the video circuitry to handle DRAM refresh ...


5

The 4116 was likely designed during in an era (or semiconductor technology node) when self-timed-delay pre-charge-evaluate NMOS logic cascades were common. (e.g. rather than synchronously or edge clocked CMOS) The bit-line sense amps and wide column select mux had to consist of a large total gate area. Thus it would take quite awhile to precharge all of ...


5

The Vic20 was not the last consumer product to use static ram on the main system board. In the mid 90's a Socket 3 (486 class) motherboard was created by Ocean Technology octek.com - defunct. The HIPPO-DCA2 motherboard which required at least one 4MB 72-pin SIMM of something called DynamiCache RAM in the first 2 slots. DynamiCache was a built from high ...


4

[Partitial answer about how it supports FPM RAM - I still need to look up the manual for timing details] Support for (Fast) Page Mode RAM (*1) The CPU supports N and S-cycles (ARM lingo) or Non-Sequential and Sequential cycles. The first access to any memory is always an N-cycle optional followed by S-cycles. To handle this the original ARM provided a signal ...


3

About that video thing: Early chips have a 7bit refresh, so you have to access all rows in a 2ms frame. You could swap some address lines to achieve more (physical) rows access per cycle. In an extreme case, you can swap A0-A6 and A7-A13 completely, so for linear access will be each byte stored in a totally different physical row. Et voila, you have a "...


3

Well, if the remaining circuitry is done, you may want to simply put pulldowns at the read data input pins. With the chip programmed as usual this should produce an all black frame. While not displaying much on a CRT it should at least synchronize. Some Chinese analogue/HDMI converter should as well report synchronisation (and display a scaled up black ...


3

Back around 1982, 1983 a friend of mine built a simple scanner using a 16k de-capped dram, probably a 4116. This was used on a Nascom 2 computer with a Nascom IMP dot matrix printer. The dram, along with a small bulb were fitted to a small cup which was attached to the print head. A sheet was put in the printer and software scanned by just printing spaces ...


3

The speed rating of asynchronous DRAM devices is usually (as in this case), the "RAS access time" or tRAC. This is the minimum guaranteed time for data to appear at the output after /RAS is provided with the row address, noting that this process also requires /CAS to be provided with the column address at some intermediate time. The speed at which you can ...


3

Static RAM stores the information by using a flip-flop for each bit. This require several (from 4 to 8 depending on the circuit) transistors but has the big advantage of being static i.e. the information stays stored as long as the circuit has current. Dynamic RAM uses a capacitor as a storage device, this has the big advantage of being much smaller than a ...


3

The inverse perspective is to consider that ARMs were optimised for relatively slow memory (FPM DRAM), compared to contemporary pure RISC designs such as SPARC and MIPS which were designed for high frequency (40MHz or more) in "expensive" computers with caches. As the target frequency was slower, ARM could afford more complex instructions than these RISCs (...


2

I found this interesting resource that appears to list the introductory pricing when devices appeared. Some items are listed as DRAM (I suspect that this is all forms of RAM). This is not a complete answer but it is way too big for a comment. One thing to keep in mind (particularly with semiconductors at the time as consumer electronics was becoming ...


2

As others have pointed out, the Cromemco Cyclops turned this into a (hobbyist) product. I've also found I could get reproducible transient bit flips in an unprogrammed EPROM. Shine a laser pointer onto the chip, and the cells under the light will flip, then flip back when the light goes away. I'm not sure of the mechanism, and I don't even remember whether ...


1

I will venture a guess. Imagine /CAS and the address bus are both registered outputs clocked by the same clock. The negative setup time allows a slight clock-to-output propagation delay discrepancy between the two outputs where /CAS falling may precede the address bits becoming stable. Moreover, there are other factors which may add propagation delay to ...


1

(Preface: leaving out the title column makes reading tables it a bit hard) It's all about translating labels and numbers into meaningful sentences. And there are different ways to tell a fact, and thus more nuanced details. Timing does describe relations. Here it's about the fact, that CAS must be released at least 20 ns before RAS can be pulled again. It'...


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