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14

Intel manufactured its 1-kilobit 1103 RAM on an 8 μm P-MOS process. Through most of the 1970s, DRAM was made from NMOS. The first successful CMOS memory was the Hitachi HM6147 SRAM, a 4-kilobit chip which used a 3 μm CMOS process. This was not the first 4-kb chip on the market (it was preceded by, among others, the Intel 2114 SRAM), but it’s more comparable ...


6

Well, depends on the definition of dual port. After all, all 9918ff based machines can as well be classified as dual ported. Similar PC graphic cards, like VGA. Beside that, the most most important reason was No need to do so. Early 8 bit CPUs were not only slow enough (compared to RAM) to allow interleaved video and CPU access on a fixed schedule, it as ...


5

Was 4 ms the typical figure for standard DRAM chips? Only starting with 128kbit and 256kbit chips. Many earlier chips (16kbit, 32kbit, 64kbit) and some 128kbit chips were documented as requiring a 2 ms refresh cycle; see these tables for details: 4116, 4132, 4164, 41128, 41256. The fact that many computers used the video circuitry to handle DRAM refresh ...


5

My recollection was that 4 kbit and 16 kbit DRAMS were being manufactured in volume around roughly circa same time frame as when 8 micron NMOS fabrication was common for other stuff. This web site seems to support that hypothesis: https://en.wikichip.org/wiki/8_µm_lithography_process


3

About that video thing: Early chips have a 7bit refresh, so you have to access all rows in a 2ms frame. You could swap some address lines to achieve more (physical) rows access per cycle. In an extreme case, you can swap A0-A6 and A7-A13 completely, so for linear access will be each byte stored in a totally different physical row. Et voila, you have a "...


3

Well, if the remaining circuitry is done, you may want to simply put pulldowns at the read data input pins. With the chip programmed as usual this should produce an all black frame. While not displaying much on a CRT it should at least synchronize. Some Chinese analogue/HDMI converter should as well report synchronisation (and display a scaled up black ...


3

The IBM PS/2 model 30 (and it's variant, model 25) use 64K of VRAM in their MCGA video system. They manage to display the 256-color VGA graphics mode (requiring around 12.6MB/s streaming to the monitor) with an 8-bit data bus, whereas the VGA card requires a 32-bit data bus with its single-ported data RAM to provide enough bandwidth. The video RAM chips are ...


1

Given packaged component costs at the time, for a given performance target, it was cheaper to time division multiplex either a wider or faster memory bus than to procure dual ported chips (much lower volume and/or higher pin count packages, synchronization circuit costs. etc). Pins were not free.


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