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It appears that A0 through A6 operate correctly, but A7 though A9 (I've not tested the rest of the upper bits) are only active on the clock edge. Doesn't that exactly look like refresh cycles? :)) Basic Z80 bus behaviour, here especially the M1 cycle: Z80 timing is structured in Machine cycles (M-states). A machine cycle consists of several Clock cycles (...


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The 64KB of RAM for the 65C102 co-processor is provided by eight MB8264 64k x 1-bit chips. Each chip provides one bit of memory for every address, meaning that all eight chips are used for every memory location. In many instances, the failure of a RAM chip will affect all memory locations (including the 6502's page 0 registers), meaning that the co-processor ...


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