There are many issues here.
As it is already said in comments, decoupling capacitor is a must!
555 (non-CMOS) timer output is very much like the output of TTL ICs, however Z80 requires a firm logic one. When feeding Z80 clock pin from a TTL output, you should use pullup resistor of 200..500 Ohm.
NMOS Z80 uses dynamic logic, that means it has some minimal ...
It appears that A0 through A6 operate correctly, but A7 though A9 (I've not tested the rest of the upper bits) are only active on the clock edge.
Doesn't that exactly look like refresh cycles? :))
Basic Z80 bus behaviour, here especially the M1 cycle:
Z80 timing is structured in Machine cycles (M-states).
A machine cycle consists of several Clock cycles (...
I'd just like to expand on a couple of points in lvd's excellent answer.
You might get by with just using a jumper wire to short the reset pin to ground for a brief moment after you've powered up the CPU. It's worked for me, but if you're having problems it's best to build a proper reset circuit.
Many CPUs have a minimum length for the reset ...
The 64KB of RAM for the 65C102 co-processor is provided by eight MB8264 64k x 1-bit chips. Each chip provides one bit of memory for every address, meaning that all eight chips are used for every memory location. In many instances, the failure of a RAM chip will affect all memory locations (including the 6502's page 0 registers), meaning that the co-processor ...