35

The PDP-10 had 'byte instructions' that could process a sequence of bytes of size 1 to 36 bits. The byte pointer was a word containing an 18-bit word address (and the usual index/indirect indications) plus position and size of the byte within the word. It was common to use 7-bit byte sequences for ASCII text, which gave 5 characters per word and one (...


31

The main issue with the 80186 isn’t with the CPU core itself, but with its integrated peripherals: they aren’t compatible with those used in the IBM PC, and they aren’t integrated in the same way either. The IBM PC uses an 8237 DMA controller at offset 0x00 in the I/O address space, an 8259 PIC at offset 0x20, and an 8253 PIT at offset 0x40. The 80186’s ...


27

PIC: 7 bit address space The Microchip PIC family of CPUs specifically the 10, 12 and 16 series have 7 bits of address space. While 7 bits is not exactly 8 bits this shows that there are commercial CPUs still on sale and still widely used that have less than 8 bit address space (they are used for example for power management on some Macs and are the most ...


21

Short answer: If you are content with beeps, no. If you want arbitrary sound, yes. There's three ways to get sound out of the PC Speaker: Put the timer chip into square wave mode and send frequencies (actually countdowns) to the timer chip. This is cheap and what's used for most PC Speaker sound effects in games. 140Hz is a popular rate to do it at. Set up ...


19

That paragraph should be understood in the context of the preceding paragraph: The PC speaker was often used in very innovative ways to create the impression of polyphonic music or sound effects within computer games of its era Effects such as those used in Pinball Fantasies in particular involve very rapid changes to the sound output by the PC speaker, ...


19

The KENBAK-1 has 256 bytes of memory. I'm not certain whether it had an 8-bit PC. https://en.wikipedia.org/wiki/Kenbak-1


17

Full disclosure: I worked on the x87 FPU of a 486-class CPU at a math-coprocessor company in the early 1990s and thereafter worked at AMD, where I was on the 3DNow! design team and the design team for the FPU of the AMD Athlon processor (also known as K7). The x87 FPU never acquired a flush-to-zero mode. In fact, denormal support was one of the major ...


14

The VT52 text terminal certainly doesn't qualify as a full computer, but it does have a processor running software out of a ROM. The RAM holding the displayed text is 2048 7-bit bytes. The character generator ROM is also 7 bits wide.


13

But was there anything other than video that was a source of hardware compatibility issues in the first wave? Or put another way: after video, what was the second most common source of compatibility issues for the semi-compatible DOS machines of the first wave? On the software side I'd say sound may lead a tiny bit before any other hardware device - then ...


12

Swapping byte lanes on the physical bus would, in any case, only have an effect on naturally aligned data in memory, which happened to be the same width as the bus. Swapping the lanes of a 16-bit bus doesn't solve the problem for 32-bit data, nor on a 32-bit bus for 64-bit or 80-bit data (the latter being associated with floating point). So that is not a ...


12

The first that comes to mind is Cypress' M8C core used in the PSOC-1 series. While it has a 16 bit program address space (and thus 16 bit jump instructions), its data as well as the register space are each strictly 8 bit. Implementations do use up to two sets of 256 registers and may offer several sets of 256 Byte banks. From the manual: The M8C is an 8-bit ...


11

I would tend to favour "conceptual simplicity" rather than trying to strictly minimise any physical parameter. Observe that some low-cost computers managed to get away with a 1-bit ALU while supporting reasonably wide data words, eg. the PDP-8/S and the LGP-30. They did this using a bit-serial architecture which was largely invisible to the ...


10

Aspects I recall, perhaps influenced by the area I was working in at the time: Video display (as you mention) Serial ports Timer interrupt I only had to work with "near-compatible" machines a few times before everything went to "100% compatible" for most hardware interfaces.


9

Yes, the sector size is software-controlled, to a certain extent. Every FDC command involving sectors or tracks takes the sector size as a parameter. The size is specified as a bit shift applied to 128, so sector sizes are of the form 128 × 2n (usable values go from 128 to 4096 on the original PC; there isn’t enough time to fit an 8KiB sector in a track ...


8

It was never fully developed in the sense that a complete system was built, but it was made into a card that plugged into the back plane of a Sun 3 system. We had one, and our card is shown here: Ours is now in the (local) Computer Museum . Unfortunately most of the software details are lost in the fog of past memories. However, good information is shown ...


8

Not strictly an answer, but there were some early computers with very limited addressing. The Harwell Dekatron computer, which operated entirely in decimal, had an address space of 100 words, of which 90 were RAM and the other 10 were devices. Programs were usually run directly from a paper tape device (for which the tape, rather than the PC register, was ...


7

Hint: It would be great if you could extend your question not only with the number of bombs, but as well the setup and conditions used to produce them. I understand bombs are sort of code indicator of what is malfunctioning in the system, Jup, they are, so it would be nice if you could tell how many you see, as that is essentially the error code. similar ...


6

I assume the main cpu s themselves were not advanced enough to decide when and how to use that spare memory themselves. A CPU by itself doesn't "decide" to use memory for something. That's the job of a program, whether it's running from ROM ("firmware") or RAM ("software"). The examples you give are clearly examples of programs being aware that they ...


6

No, for many reasons. The yellow connector that you are talking about is called composite video. It's called "composite" because it combines several signals: vertical synchronization, horizontal synchronization, blanking, luminance (the black-white part), and chrominance (the color part). No model of Macintosh bothered to combine these signals, ...


6

Since you mentioned the Amiga in your question, it ought to be relevant as to how this problem was solved efficiently on that system. As I understand, the "glue" logic for the Bridgeboards consisted mainly of 128KiB of dual-ported RAM accessible by both the Intel CPU on the Bridgeboard and the Amiga's 68K. This would be sufficiently large to buffer ...


6

No. The Mac SE vertical and horizontal scan frequencies (designed into both the CRT yoke and the analog sweep generator circuits) are different from NTSC (and PAL) composite timing. And the Mac SE analog board requires separate vertical and horizontal sync inputs, not just a video signal. The analog board sync inputs need to be at TTL voltage levels, ...


6

The second-generation Soviet computer Minsk-32 (the series size is 2889 machines, 1968-75, civilian use, one of the rare early mainframes noted for use in Antarctica) used a 37-bit word and 7-bit representation of alphanumeric characters (5 in a word). Yes, the concept of "bytes" is difficult to apply to a similar old computer (which continued the ...


6

The Intel 8048 which was used in the Magnavox Odyssey2 had an 8-bit external address bus.


6

An advantage which FPGA emulators generally share with vintage hardware is the ability to use devices that interact with the hardware in ways that are very timing-dependent. For example, if one has a game cartridge for the NES which triggers an interrupt every time the first line of data for a particular sprite is fetched, a console that reads out the ...


5

This take a little more circuitry than the OP, in that the byte-swapper has to make use of the Function Code bus lines (FC0, FC1 and FC2) to distinguish between data transfers and instruction fetches. Bytes should only be swapped for data transfers; applying byte-swapping to instructions will wreck the execution of software.


5

Stephens Answer points out most details, I belive it's worth to mention that the 80186 is not incompatible with the IBM-PC's structure/hardware per se. The CPU core works for all details like a 286 in real mode, with the same additional instructions and exceptions, as there are: Instructions: Array Check (BOUND) Integer Multiplication Immediate 8/16 (IMUL) ...


5

"Core memory" comprises three technologies. All disappeared with the introduction of semiconductor memory. Magnetic-core memory was a nonvolatile, rewritable memory made of wires threaded through ferrite toroid cores. The cores are arranged in a grid, with wires along the rows, columns, and diagonals of the grid. By passing sufficient current through the ...


5

TL;DR: For example the TI-99/4 system did store all BASIC code and variables within the 9918's RAM. The Long Read: The TMS 9918 acted on its own video memory, seperate from main memory. The memory could be accessed by an external system (aka main CPU) via a port, by setting an address and reading or writing a byte or stream of bytes. There was no predefined ...


4

You could theoretically create a system with 3-bit words for the Brainfuck programming language. That language is technically Turing-complete, although quite tedious to program. It is a popular language for the Code Golf StackExchange. A processor for Brainfuck needs the following: Memory to store data. Wikipedia suggests a minimum size of 30,000 bytes, ...


4

Amusingly, I posted about my design for a processor that's as simple as possible while still being useful over on the anycpu forums just this morning... Summarising: My design uses 14 standard chips (including a 16-bit wide ROM for the instruction data which may need to be replaced with 2x8-bit ones depending on availability). It's a very limited design, but ...


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