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3

I suppose it depends what counts as "mass produced". One can implement the same kind of circuits used in IC mask ROMs on a PCB with diodes. This is a PDP-11 boot ROM from the early 1970s. (Source of image and short article about the board here.) You place a diode where you want your bits to go and solder it in. DEC also sold blanks, where you ...


0

A bit expensive, but there is this option: https://icomp.de/shop-icomp/en/produkt-details/product/ace2.html#filter=* Updates the Agnus to have 2 Meg chip.


3

IBM's TROS (Transformer Read-Only Storage) and CCROS (Capacity Coupled Read-Only Storage) both were ROM-alike, entirely free of semiconductor material, and basically one-time programmed like punch tape (it could be re-programmed by exchanging the tapes with re-punched ones, and CCROS even shared the same format with IBM punch cards for its plastic sheet, so ...


13

According to Willis82 at https://www.tapatalk.com/groups/nintendo_64_forever/rumble-pak-mod-t6706.html Nintendo actually did this to kiosk rumble packs so shop owners wouldn't have to change batteries. They even went so far as to glue the battery doors shut. It's ok to run a rumble pack this way but never run 4 controllers with 4 modified packs, it draws ...


0

First off, Commodore acquired MOS Technologies in 1975.... before the PET by a few years. Commodore had made licensing deals with Rockwell and Syntertek and others as second source licensees of their 6502 cpu which even in 1975 with Apple and the Apple I and upcoming and potentially popular Apple II (which we know became popular) was a way for Commodore to ...


3

The IBM PS/2 model 30 (and it's variant, model 25) use 64K of VRAM in their MCGA video system. They manage to display the 256-color VGA graphics mode (requiring around 12.6MB/s streaming to the monitor) with an 8-bit data bus, whereas the VGA card requires a 32-bit data bus with its single-ported data RAM to provide enough bandwidth. The video RAM chips are ...


1

Given packaged component costs at the time, for a given performance target, it was cheaper to time division multiplex either a wider or faster memory bus than to procure dual ported chips (much lower volume and/or higher pin count packages, synchronization circuit costs. etc). Pins were not free.


6

Well, depends on the definition of dual port. After all, all 9918ff based machines can as well be classified as dual ported. Similar PC graphic cards, like VGA. Beside that, the most most important reason was No need to do so. Early 8 bit CPUs were not only slow enough (compared to RAM) to allow interleaved video and CPU access on a fixed schedule, it as ...


1

This is how my emulator stores this instruction: ---------------------------------------------------------------------- |opc T0 T1 MC1 MC2 MC3 MC4 MC5 MC6 MC7 mnem | |--------------------------------------------------------------------| |ED43L1H1 20 00 M1R 4 M1R 4 MRD 3 MRD 3 MWR 3 MWR 3 ... 0 LD (U16),BC| ----------------------------...


4

Comments have already covered that the CPU manual should answer all your questions, but above and beyond that, immediate observations: ld (nn), bc is encoded as ed43 so that's two reads; the actual address, 0x1000 is also two bytes long, so that's another two reads; bc is two bytes long, so that must be two writes. In total that's six memory accesses, from ...


19

Without detailed documentation on the PDP-8 design process, we cannot say for sure. I suspect that while they may have briefly considered it, it was never a serious prospect. The PDP-8 is just the PDP-5 redesigned electronically. The PDP-5 was introduced in 1963 as an even-more-reduced version of a computer compared to the PDP-1 and PDP-4. The PDP-1/4 did ...


7

I'm going to say no. The PDP-8 was chiefly designed for compatibility with the PDP-5, and this machine also had no hardware stack. There is not enough room in the instruction space to add push and pop instructions either.


5

Worthy of mention is the rise of the microprocessor- notably the 4004 which was designed for mostly numerical operation in calculators. Whether the step to 8 bit architecture was inevitable is open to debate, but once memory ICs started being produced in 8-bit forms, it would be difficult to justify anything other than 16-bit as the next step. Looking at ...


37

there some particular design theory or constraint that made a 32-bit word size attractive for IBM to migrate to? It all comes down to the most basic data type, addressing constrains and, less important, reuse of existing memory technology. The byte size had to be a multiple of 4, as needed to accommodate BCD numbers without wasting space. So 8 was chosen ...


6

One small reason is that you can access memory as a bit array without needing to divide (or do a modulo). Just use the bottom N bits for the byte or word or data cache line position or shift, and the rest of the bits left over as a memory address offset. Which can be done in hardware for free if needed.


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