54

Illegal opcodes were just instructions that hadn't been fully defined by the chip designers – a little like Undefined Behaviour in C, but much more predictable. Many people called these "undocumented instructions", because they functioned just like ordinary instructions, on the particular versions of the particular chips on which they are found. There was no ...


52

LOADALL is an undocumented instruction available on the 80286, 80386 and some 486 clones. It provides a means to load all the CPU's registers in one operation, including normally-inaccessible registers (descriptor caches). Its significance is that it allows extended memory to be accessed on a 286 without switching to protected mode. On a 8086, memory is ...


51

For the most part the Z-80 extends the 8080 instruction set. If we consider just the 8080 instructions themselves there are a few incompatibilities: Overflow flag. On the 8080 bit 2 of the flags register only reports the parity of the accumulator after an ALU operation. On the Z-80 it reports parity for logical operations and overflow for arithmetic ...


47

MOV changes the N, Z and V flags according to the copied data. JMP doesn't do that. It means you can run e.g. arithmetic operations somewhere, then jump to another location for the compare routine. Also JMP appears to be 1 cycle faster. The handbook says JMP takes 1 to 3 cycles while MOV take 0 to 4 - maybe because it doesn't set the flags.


46

There are no technical reasons, as any order would work and result in the same amount of gates. More likely it originated in the process by which the 8086 was developed. A main goal was to allow easy conversion of 8080 programs, so the development of the 8086 structure started out from a 8080 programming model. 8080 registers were ordered as 16 bit pairs in ...


46

Very simple: Because there was room for an address and it improves performance a lot. Or as the manual puts it: It is important, however, for the programmer to realize that the simplest method of programming (using sequential drum location for succeeding instructions) causes the machine to waste a large amount of time waiting and searching. To start with,...


45

The opcodes in your list are all only 16 bits (plus the extra bytes for address calculation) and you'll notice that they all begin (in hex) with Dx where x >= 8. This is because, to the 8086, any instruction whose first byte has the bit pattern 11011xxx was deemed to be an 8087 coprocessor instruction. When the 8086 encountered a floating point opcode, it ...


45

Setting and clearing carry, the decimal or interrupt flags is useful: the carry flag because the 6502 offers only add and subtract with carry; the decimal flag because it changes the mode of the processor; and the interrupt flag because it masks or unmasks the maskable interrupt. Conversely, explicitly setting and clearing the other flags mostly isn't ...


44

It might be better to think about it this way: On the 80186 and above, a new thing was defined called an "illegal instruction", and this new thing came with a new behavior -- a #UD exception that was generated when one was encountered. Before the 80186/80286, there was no such thing as an illegal instruction, just undocumented ones. Your question then ...


42

Besides the flags, and differences in cycle count, the more important difference is that JMP x uses the effective address of x, while MOV x,R7 uses the value at x. In other words, there's one level less of indirection, similar to the LEA and MOV opcodes for the x86. So JMP R1 faults, and JMP @R1 is equivalent to MOV R1,R7. This means one can use JMP d(R7) ...


41

Some uses for a bitshift operation: implementing a more efficient multiplication than repeated adding implementing division algorithms implementing an algorithm for exponentiation of integers by other integers bitwise algorithms e.g. "how many one bits in this integer" fast multiplication and division by powers of 2 including indexing arrays of integer ...


41

Early MOS documentation (KIM-1 Programming Manual, Synertek SY6500/MCS6500 Microcomputer Programming manual, etc) states: The BIT instruction actually combines two instructions from the PDP-11 and MC6800, that of TST (Test Memory) and (BIT Test). ... In addition to the nondestructive feature of the BIT which allows us to isolate an ...


37

Besides the matter of semantics and personal taste, there’s a much more practical reason: some instructions sets claim to be copyrighted, as the Wikipedia Z80 article states: Because Intel claimed a copyright on their assembly mnemonics, a new assembly syntax had to be developed for the Z80. This time a more systematic approach was used. So, I think the ...


31

An instruction set can be considered as a Huffman coding of an idealised instruction stream. So the question is really asking which CPUs have a good balance of short encodings for common tasks to longer encodings for rare tasks. However, it is not sufficient to just look at the encoding of individual instructions because a RISC instruction generally does ...


29

I'm having a hard time picturing a use for this [BIT] It's mainly an I/O issue. The 6502 is in many ways designed especially for control/embedded applications and BIT is a part of this. 6500 specific IO-devices are designed to report any service conditions on bit 7 (and 6). For example the 6522 will set bit 7 of the Interrupt Flag Register when an ...


29

Because "move" is the typical necessary function It isn't always this way, of course, but especially with earlier CPUs, there were limited destinations for data from a particular operation - e.g., arithmetic results could only be in certain registers. Or in the other direction, certain functions could only operate on a few locations, typically registers or ...


28

TL;DR: It is all about making one of the most important instructions as performant as possible, while keeping everything manageable for tools at the time (plus a little bit of dogma). The branching is thus the most optimized instruction of the whole 6502 design. In addition, long branches are not really in demand (*1). Of the 116 branches used in the ...


26

There is simply no need for setting Overflow. The same is as well true for Negative/Sign and Zero. No operation will be influenced by any of them, it's only used to signal an overflow during ADC and SBC (well, and BIT for testing bit#6). In fact, the question is rather, why there is a CLV present, as there is no reason, within the boundaries of the ...


25

Per Zilog's Z80 user manual: Two BCD digit rotate instructions (RRD and RLD) allow a digit in the accumulator to be rotated with the two digits in a memory location pointed to by register pair HL (See Figure 10). These instructions allow for efficient BCD arithmetic. Given that DAA exists for addition and subtraction, I'm going to hazard a guess that the ...


24

If you go back a lot before the x86, this technique wasn't unusual at all. In fact, writing programs using printable letters and symbols was pretty much the norm for early computers, except that there was a number of encodings for words of varying bit size, and that encoding was not ASCII. Examples: On the IBM 1401 (1959), a program that looked like ,...


23

But how instructions like DEC, DEX and DEY works ? By adding $FF provided by the precharged internal data bus to the register content. In Detail: The internal databus is precharged with $FF during PHI2 (*1) During the next phase it's loaded into the B register (signal DB/ADD) At the same time the index register is transfered via SB (*/SB) to the A ...


22

A good example would be reading from the floppy drive on the C64. The incoming clock and data signals of the serial bus are (perhaps not accidentally) wired to bits 6 and 7 of port A on CIA#2, appearing at $DD00. BIT $DD00 samples both inputs and stores them in the N and V flags. Jumping back conditionally with BVC $-3 waits while the clock is low, as ...


22

The TRS-80 series is Z80 based, and Z80 uses, like all 8080 offspring (*1,3) a separate address space for I/O. It allows easy decoding for I/O. Thus memory address 0000h is different from I/O address 00h. On logical (program) level, access to either address space is selected by the instructions used. Memory instructions always access memory address space ...


21

Ken Shirriff has, as so often, a nice table to start with - especially nice to detect the 'undocumented' ones. All opcodes in lower case are 'undocumented'. With sorting his table according to the 'octal' (2-3-3) decoding logic the 8085 uses (*1), the first are nicely grouped where the 8080 only decoded NOP: (NOP - Not undocumented, but on the 8080 it ...


20

This document calls out some differences: http://www.msxarchive.nl/pub/msx/mirrors/hanso/datasheets/chipsz80leventhal3.pdf Z80 uses P flag for 2's complement overflow, where 8080 does not DAA instruction corrects both subtraction as well as addition on Z80, but addition only on 8080. Z80 rotate instructions clear the AC flag, but the 8080 does not. Also, ...


18

The HALT condition does (at least on retro CPUs) not consume considerably less power than normal execution does. One very obvious use case is synchronizing program flow with external (hardware) events. The main use case of the HALT instruction is thus "wait for an interrupt". A prominent example outside embedded systems is synchronizing video output with ...


18

[...] had these opr instructions, which contained many bitfields which encoded something like "subinstructions"[...] What you describe is basically a (V)LIW instruction format - at least that's what it might be called today. That's what computers started out with. Separate bits for each function to be applied to the value addressed. The DEC is somewhat of ...


18

TL;DR It's all about getting systematic, easy to memorise mnemonics, which may reflect some underlaying structure, but most important ease practical use. Exact language is not always a handy one - except you're asking a lawyer :) So why call the instruction "move"? Oh, the age old copy-vs-move question. A beloved friend :) There are many different, ...


18

To directly answer the question: there is no difference whatsoever on the software side. The CPU core and indeed the die inside the package is exactly the same, just different pins are bonded out in one specific corner. The actual difference is entirely in the clock generator. The non-E version has oscillator-driver pins for directly attaching a crystal, ...


17

The PDP-7 was a one address machine. All instructions occupied 18 bits. The operations that manipulated the accumulator didn't reference memory, and therefore didn't need an address. But the address bits were in the instruction anyway, because all instructions were encoded in an 18 bit word. So why not use these unused bits to get more use out of the ...


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