38

The instruction decode is quite simple on the 6502. If we call the bits in the opcode byte aaabbbcc, then one of the first things that happens is that cc, the two bits you're talking about, gets converted into a 1-of-3 signal which selects the register. This signal is called G, and is computed like this: A is true if the bits are 01 X is true if the bits ...


30

Below are some architectures with odd word sizes: Apollo Guidance Computer: 15-bit Autonetics D-37C Minuteman II Guidance Computer: 27-bit Electrologica X1, Electrologica X8: 27-bit Calcomp 900: 9-bit Gemini Guidance Computer: 39-bit See https://en.wikipedia.org/wiki/Word_(computer_architecture) Note that the register size may be a multiple of the word ...


23

The opcodes are already sorted that way. Just a bit less obvious and schoolbook-like, but optimized to allow compact decoding. It is all about space saving. Real chip space and (potential) transistors that is. It's well known that the 6500 design was all about cost saving and the most important factor in chip production cost is its size. Smaller chips mean ...


21

The TLE instruction is a modification of the TLU instruction. TLU (Table LookUp) (Opcode 84) compared a word with a series of consecutive words on the drum and finished as soon as an entry was found being equal or higher. It was meant to find a point in a sorted list. TLE (Table Lookup Equal) (Opcode 63) is a modification of TLU stopping only when equal, ...


17

TL;DR: TS, CAS and CAS2 work thru bus locking CAS2 was introduced with the '020, the '030 had to have it for compatibility While the 'cost' of locking for a complex operation is high, it's not higher than for simpler versions doing the same CAS2 is overall more performant than a series of CAS/TS instructions [While all 4 points are valid, the second ...


16

The EDSAC (started in 1947) had been intended to have 18-bit words, but due to timing difficulties in the mercury tanks, it ended up with only 17 (= 18 - 1) bits usable for word operations, or 35 (= 2 x 18 - 1) bits for double word operations. True, this was "memory" and not "registers", in modern but not contemporary parlance. ...


15

The Elliott 803 computer was 39-bit. The instructions are 19-bit with two per word plus a single bit modifier for the remaining bit. Elliott 803 Wikipedia


12

The 1955 manual for the IBM 704 on page 7 talks about data representation in the computer. When a word is interpreted as numerical data, the zero position acts as the sign of the word. (…) When a logical operation is performed on a word, the word is interpreted as a 32-bit signless number. As an algebraic (signed) binary number, a word can represent (…) In ...


12

The HP-3000 first introduced in 1972 was a 16-bit stack-based architecture that included an XEQ instruction that would treat a word on the stack (between TOS and 7 words below that as selected in the instruction) as a regular instruction and execute it. This was utilized in some calling conventions where you needed to execute a different version of the EXIT ...


10

To touch on the underlying question: I do not see a reason why this has to be so. There is none. Register width is selected for 3 basic reasons: Fitting the purpose by being able to hold (usually overlapping) the most important data type, or the most basic data type, or a memory word. Fitting (CPU) building elements, by being multiples of ALU element ...


9

TL;DR Too complicated for not much benefit. You ask why not include an execute instruction. The reason is quite simple. Since around the time you observed the absence of this kind of instruction, the CPU's got more and more optimized in their memory access. Code access was separated from data access as the access pattern are quite different. To execute a ...


8

Asking about "the first architecture with an FPU" invites question-begging. Did the Zuse Z1, which used floating-point numbers for all arithmetic, "have an FPU"? The ENIAC did not have an FPU; it used a ten-digit decimal notation, with no floating-point features. The IBM 704 had one as standard equipment in 1954. It had various floating-...


8

Yes. Sort of. The KDF9 had an accumulator stack (the 'nesting store' or nest) which was mostly made of fast (1µs read, 1.5µs write) core - the top 3 elements were in fast registers, with 16 words of core underneath. Arithmetic was done on the top elements of the nest, popping off operands and pushing the result in the usual manner. Though the top cells were ...


7

I haven't found an architecture designed after 1976 which includes such an instruction. TL;DR: There is no use case for next to all later GP architectures. The Long Story: Because next to all general purpose (GP) architectures developed since then followed a rather simplified structure that holds all parameters that can/may be modified in registers (or ...


6

This is a little bit outside the scope of the question. It's not really arithmetic instructions (though they are common instructions, and some of them do involve arithmetic), and the architecture in question isn't very "retro". But anyway, maybe it will be of interest to someone. In the ARMv8 architecture, circa 2011, most instructions write to ...


5

I was going through the literature produced by Zilog in the 1980s and noticed that in their "Microprocessor Applications Reference Book, Volume 2" (1983), nicely scanned for us by BitSavers, they attempted to compare Z80 vs 6502 (see Section 2 "Z80 CPU vs 6502 CPU. Benchmark report"). Given that this comparison was produced by one of the ...


5

(Another "what was the first" question where it's basically impossible to answer it unless one goes through all computer instruction sets ...) One example of the usage of "logical" is the IBM 7090 (1959), as one can verify in the manual where the shift instructions are listed starting on page 31: ALS Accumulator Left Shift ARS ...


5

Beside the detail, that the ENIAC wasn't 'programmable' in today's sense, but wired like a tabulator? Also, it wasn't 'with' a FPU, but only a FPU - if that's applicable at all, as ENIACs format wasn't float, but chunks of 10 digits up to interpretation. It was more of a configurable calculator than a computer in today's sense. Machines like the ENIAC as ...


5

If you are into art, you may have heard of the MIX computer from The Art of Computer Programming. Its words are 5 bytes (not like any other architecture's bytes) plus a sign. So are registers A and X. When implemented in bases 4 and 64 to 100, each byte has an odd number of bits.


4

Great historical examples here, but I missed the one-bit slice processors that were developed in the 1970-s, that went on to the (Intel) four-bit and 8-bit processors that are better known. One (1) is the (ultimum) oddest number for CPU register size, you can't go much lower, while the current craze is to crunch as many bits at a time as possible. Examples: ...


3

Did any computers of that era, provide such a variant instruction? Kind of, the /360 (1964) implemented a Test and Set (TS) instruction for process synchronisation. A byte addressed was read, tested for zero/not zero (*1) and written back with all bits set (X'FF'). This write back was done not by the CPU in a follow up write access, but by the memory ...


2

Fairchild F8 There is "add to accumulator" but no subtract. There is "decrement register" but no "increment register" There is "increment accumulator" but no "decrement accumulator"


2

This looks like a single genius strike Na, not really, they are essentially the flags that can come out of an ALU, or more correct, they are the outputs that can be brought directly out of an ALU. Just imagine the idea is to separate instructions and branching to reduce instruction set size and improve reusability. Looking at an ALU with this goal in mind ...


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