20
votes
Accepted
Carry handling during address generation on a 6502
The manual says that the branch instructions do not affect the carry flag. However, my understanding is that some carry handling may be required when adding the relative branch offset to the program ...
- 198k
12
votes
Is there a CPU ISA preferring a test for the value of one over testing for zero?
ISZ on the PDP-8.
In the special case where the flag will only ever be tested once (because the test trashes the flag), the PDP-8 "ISZ" instruction distinguishes the value -1 from all other ...
- 1,054
10
votes
Null-terminated strings on the PDP-7?
a post that states that Unix uses null-terminated strings, ASCIZ, because it was a feature of the PDP-7.
Yes, ASCIZ strings are especially supported by the PDP-7 due existence of the SZA instruction ...
- 198k
10
votes
Accepted
Null-terminated strings on the PDP-7?
You are correct. There is no special support on the PDP-1/4/7 for ASCII null-terminated strings. Or strings of any kind, really. It's up to the programmer to decide how they want to represent ...
- 13.2k
9
votes
What are the “building bricks” of ARM’s design that this magazine article is referring to?
Such short and rather terrible wording leaves a lot to be desired. In addition it's noteworthy that the article is most likely not well researched, as it states that only IBM has used RISC in an '...
- 198k
9
votes
Would compare-and-branch have added an extra cycle on ARM-1?
Remember that classic AArch32 code has conditional execution of most instructions, which more or less demands a condition code register in simple implementations. Once the ARM designers had included ...
- 9,883
7
votes
Would compare-and-branch have added an extra cycle on ARM-1?
Yes, it would add a cycle.
How do you branch on ARM?
add pc, pc, #8
That's a bit of an over-simplification, but the point is that ARM was meant to be purely orthogonal, that is, the program counter is ...
- 301
7
votes
Is there a CPU ISA preferring a test for the value of one over testing for zero?
In the General Instruments PIC architecture families that debuted in the 1970s, and were adapted into the Microchip architecture families of the same name, there is no instruction to directly test ...
- 32.8k
6
votes
Accepted
What is the purpose of the "difference of absolute values" instruction?
A variant of the compensated summation algorithm needs to perform comparisons of absolute values of the running sum and the current summand:
function KahanBabushkaNeumaierSum(input)
var sum = 0.0
...
- 17.8k
5
votes
Accepted
Would compare-and-branch have added an extra cycle on ARM-1?
The ARM1 CPU core was tightly coupled to the memory interface - it was designed to be as efficient as possible when paired with FPM DRAM, and no consideration was given to performance with a cache or ...
- 1,030
4
votes
Would compare-and-branch have added an extra cycle on ARM-1?
The CDC 6400 series of supercomputers, developed by Seymour Cray, are considered some of the earliest RISC-like architectures, having been released in 1964. These used compare-and-branch instructions....
- 7,857
3
votes
Would compare-and-branch have added an extra cycle on ARM-1?
It's not very RISC purist; the designers seem to have been happy to make an instruction do more than one thing,
Erm, RISC isn't about doing only one thing, RISC is about not doing complex stuff. RISC ...
- 198k
3
votes
Is there a CPU ISA preferring a test for the value of one over testing for zero?
A little contrived, but:
The PDP-11 (in all but the earliest models) has the SOB instruction:
SOB Rn, LABEL
The register is decremented, and if the result is non-zero, a branch is made to LABEL. Thus ...
- 31.6k
2
votes
Is there a CPU ISA preferring a test for the value of one over testing for zero?
The Burroughs B5000 has no way to test a complete word directly against a value, be it zero or one. Looking at the instructions (section 5), the only conditional branch operations are BFC (branch ...
- 24.9k
1
vote
Is there a CPU ISA preferring a test for the value of one over testing for zero?
I dimly recall the i960 setting aside a few bits in certain instructions so that the opcode could include a small number, possibly 4 bits signed IIRC so that values in the range -8 to +7 could be ...
- 1,075
1
vote
What motivated the weird boolean instruction repertoire of the PDP-11?
Recap:
The PDP-11 needs a full six bits per operand, which is almost a byte. This puts pressure on the opcode space, meaning it can't possibly offer all the same instructions as, say, the PDP-6 did. ...
- 71
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