New answers tagged

1

Pretty much any One Instruction Computer architecture could be described this way. In such machines, there is no opcode field, and the operation performed each time is sufficiently flexible to have several different effects depending on the operands given. If the operation implemented is Decrement And Conditionally Branch (which has been shown to be Turing ...


4

The Pilot ACE, commercialized as the English Electric DEUCE, had an instruction set which looks pretty peculiar to modern sensibilities. It had no explicit 'opcode' field, instead just source and destination addresses (as well as 'next instruction' address and timing-related fields). The address fields surely required some decoding, but then again it's ...


11

Horizontal Microcode works exactly as you describe - one bit for each possible internal control line (Vertical Microcode saves instruction bits by encoding sets of N mutually-exclusive control lines with log(N) bits, with appropriate demultiplexers in place). In theory one could use this as the primary instruction level, but of course it would be very ...


10

(Preface: The question is a bit misleading, as many of the conditions implied are not well defined. See below) First candidate: Transport Triggered Architectures Transport Triggered Architectures are not only a special case of single instruction architectures, but should this the 'no decoding' requirement quite nicely. Its only instruction is to transfer a ...


2

Another possible reason: with PC-relative addresses, you can easily relocate your program in the memory. Sometimes is a good idea to have a program you can load and run from any address (well, not really ANY, but you know...) When you program like "jump 10 bytes forward", you can easily relocate. With "jump at $12A5", you have a fix memory location your ...


13

On the 6502, the designers did this for efficiency. This is documented in the original MCS 6500 Microcomputer Family Programming Manual: If one considers that the instruction JMP required three bytes, one for OP CODE, one for new program counter low (PCL) and one for new program counter high (PCH) it is seen that jump on carry set would also require ...


25

TL;DR: It is all about making one of the most important instructions as performant as possible, while keeping everything manageable for tools at the time (plus a little bit of dogma). The branching is thus the most optimized instruction of the whole 6502 design. In addition, long branches are not really in demand (*1). Of the 116 branches used in the ...


Top 50 recent answers are included