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74

I suspect your teacher was referring to the FDIV Pentium bug, which led to a large outcry in the media at the time and for which Intel issued a recall. This bug caused floating-point division to return incorrect results in some cases. It didn’t affect only FDIV, some related instructions were affected: the other division and remainder instructions, and FPTAN ...


45

Clock to clock Tualatin Pentium 3 was a lot faster (i.e. a P3 got more done in each clock cycle than a P4). High-end Pentium 3 is available at 1.4 GHz while low-end Pentium 4 is 1.5 GHz so if you compare these extremes P3 is the clear winner. But as time went on, Northwood Pentium 4 1.8 GHz plus DDR 266 memory became common quickly while Intel constrained ...


32

The extra pins were forward-planning, on both Socket 2 and Socket 3. Most of the extra pins are used for power (Vcc) and ground (Vss), which is useful to provide more power to a CPU. The other pins are keys, a new INIT pin (F19), and signals used for enabling and controlling the write-back L1 cache. (See the socket 3 specifications in the 486 family ...


28

Stephen Kitt has already provided a good answer regarding the FDIV bug. I'll fill in some details about Intel employing logicians: Because of this bug, Intel had to replace a lot of processors, which was very expensive. Not wanting to repeat this, they hired a number of computer scientists with background in formal logic to prove the correctness of ...


25

Here’s the list of main technologies used: 4004: 10µm PMOS; 4040: 10µm PMOS; 8008: 10µm PMOS; 8080: 6µm NMOS (faster than PMOS, and TTL-compatible); 8085: 3.2µm NMOS, then HMOS (“H” variants); 8086: 3.2µm NMOS, then HMOS (in three iterations) and CHMOS (static variants); 80186: 3.2µm HMOS and CHMOS; 80286: 1.5µm HMOS (also CMOS, at least from other ...


24

The very earliest, slowest-clocked, Pentium 4 chips were slower than the fastest Pentium IIIs of the time. The PIII was available at 1GHz when the Pentium 4 was introduced, and a 1.5GHz P4 was about the same practical speed: it varied a bit, according to what you were running. However, the P4 was also available in 1.3GHz and 1.4GHz clock-speeds, and those ...


21

I found this page on the motherboard, which says they are some sort of "32-bit external memory card." What are these slots? They are exactly that, memory expansion. This is a rather early 386 board from before memory modules became a thing. The mainboard can be fitted with 1 MiB using 256 KiBit chips (41256), so any expansion has to go on cards. With (AT)...


20

Intel had a rather complex bunch of hardware to compute a floating-point quotient in a way that yielded two bits per iteration, which required having a rather large table listing all the combinations of bit patterns where part of the quotient should be 11 [rather than listing all patterns individually, the table would have had entries where each bit may be 0,...


20

The Am386 and Am486 were designed as clock-for-clock equivalents of the corresponding Intel CPUs, based on reverse-engineering and AMD’s previous second-source licenses — at least the Am386 even used the same micro-code as Intel’s 80386. The only speed advantages came from higher clock speeds (40MHz v. 33MHz) and, in some Am486 models, the use of write-back ...


19

Short Answer: At the time PCI was devised, the x86 bus had already gone a long way toward being less chip specific. PCI is maybe a clean design, but some choices for signals are still 'intelish' Moving bus definition from following what a certain CPU implementation needs toward a more generic structure opens up more ways for future CPU development than ...


15

The answer is sort of. Intel also went with a different memory subsystem, RDRAM, which had a big influence on system performance. I'll be basing my answer on the AnandTech review of the Pentium III vs Pentium 4 vs AMD Thunderbird. Let's start out by looking at performance in a popular game of the time, Quake III Arena. You can see the Pentium 4 is the ...


15

You can find here the Intel 4004 datasheet. You can see from the 4004 Instruction Set table on page 4 that the 3 nibbles of a jump target address (in ROM) are stored with the highest order nibble in the first byte of the instruction, and the two other nibbles in the 2nd byte. Thus we conclude that in the instruction set fields > 4 bits are stored with ...


13

The early-to-mid 1990s was a time where the future of the Personal Computer was very much up for grabs. Both the "Wintel" monopoly as a whole, and each part individually, where not at all set to be the foundations of the future PCs. Even if we were to assume that x86 would "win", we had OS/2 and to a lesser extent BeOS as competitors on ...


12

Nobody has really covered the technical aspects of the PCI bus. Until then most busses had been mere extensions of the CPU's memory bus. Zorro was essentially an extension of the 68000 memory bus, S-100 which was just the 8080 bus, and ISA was basically the 8088 memory bus. There were a number of issues with these early expansion busses. These busses used ...


12

I’ve wondered about this for a long time — manufacturers don’t seem to communicate FPU transistor counts as readily as CPU counts. The best I’ve found so far is a claim on coprocessor.info that the 80387 contained approximately 120,000 transistors (quite a bit more than the 8087’s 45,000 transistors).


11

Short Answer: Yes. Celeron is a sales name, and does not specify a CPU architecture or instruction set. Having said that, FCOMIP was introduced with the P6 Family, so essentially with the Pentium PRO (for workstation) and Pentium MMX for mainstream machines. IA-32 implementations before these CPUs do not feature this instruction. The first Celeron is ...


10

Is it really so simple as just getting to higher clock speeds than Intel did? Yes, it is that simple. Up and including the 486 AMD's CPUs were developed close to Intels devices, supported by in detail information provided by Intel as well as reverse engineering. AMD adapted the design to their production process. This included low level changes in how ...


8

Socket 3 did not have more pins than needed. It was designed to support the Pentium OverDrive CPUs that Intel released in the mid-1990s. These CPUs could have up to 237 pins, while the Socket 3 allowed 238 pins.


8

To add to Raffzahn's answer: I strengthen the "might not be compatible to 16-bit cards" to "are most likely not compatible to 16-bit cards". As I see the traces on the photo, there is nothing that supports the impression these slots are ISA 16-bit compatible - but also no proof they are not. A reliable tool to learn more about that board is a continuity ...


8

The original Pentium, which succeeded the i80486, was indeed the original definition of the i586 instruction set - and not x86_64. But the Pentium was introduced in 1993, and your HP machine is much newer than that. Intel has continued to use the Pentium brand for almost every x86-compatible CPU line they've made since then, to great confusion among people ...


7

Have you referred to the Intel 286 manuals yet? The 286 Programmer's Reference Manual (PDF copy on Bitsavers linked here) covers the instructions in general from a programming perspective, including a brief overview of the protected mode instructions. The Operating System Writer's Guide (Bitsavers again) deals specifically in depth with the 286's protected ...


7

Is it true that the Pentium III was faster than its successor Pentium IV? Yes and no. As usual it all depends on the time to look at, but also what is defined as 'fast'. MHz vs. Throughput vs. Bang per Buck. In the MHz game (*1) the Netburst (Pentium 4) design clearly outran the P6 (Pentium II/III; *2). In throughput it was much like with every new design....


6

Intel 8008 CPU has an internal stack, implemented as an 8 x 16-bit scratchpad. No, it's entries are 'only' 14 bit long, as all addressing on the 8008 supports only 14 bit (*1). How does it work exactly? Is there any "invisible 3-bit stack pointer"? Yes. In reality it's not a stack pointer, but selects the active PC. A three-bit address pointer ...


6

I don't know the total quantity of 'RAM' sold in those years, but according to this site the total number of DRAM chips and Bytes sold each year was:- Year million units GiB ---- ------------- ------- 1974 4.77 2.27 1975 23.15 11.04 1976 48.34 24.02 1977 80.79 49.88 1978 111.36 109....


5

Older slot 1 boards only support 66MHz front-side buses and won’t boot with a Coppermine core. Coppermines use a 100MHz or 133MHz FSB. Any motherboard officially supporting the latter should also support Coppermine. Motherboards only supporting 100MHz FSB may work with 100MHz FSB Coppermines, or even 133MHz if overclocked, but it’s not guaranteed — for ...


5

In Appendix C (on software compatibility to the 8086), the Intel 286 users manual states the following about instruction length (Page C-2): Do not Duplicate Prefixes. The 80286 sets an instruction length limit of 10 bytes. The only way to violate this limit is by duplicating a prefix two or more times before an instruction. Exception 6 occurs if the ...


4

You are getting everything wrong. The 286 has integrated segmentation unit and protected modes to allow multitasking OSes and more memory (up to 16MB). It was actually used for that purpose in early versions of OS/2 and Windows. The definition of "workstation" is arbitrary. 640kB DOS was becoming cramped, and the 286 allowed to use more memory. The ...


3

To add to the above, there was a book that I had as a teenager, published in 1966 We built our own computers by A.B.Bolt et al. ISBN 9780521093781. You can view some of the pages here https://books.google.co.uk/books/about/We_built_our_own_computers.html?id=aQ84AAAAIAAJ Yes, people did wire up components to make computers prior to 1971. These are more ...


3

There are a few details with x86 inheritance in PCI : Little Endian only. Big Endian CPUs (such as PowerPCs as default) had to adapt to that bus by using reversed endian instructions, or bus swap hardware in PCI controllers. IO address space. Competing RISC CPUs (PowerPCs, ARM, SPARC...) didn't use IO ports (well in POWER it was obsoleted IIRC), only memory-...


3

The answer to your question 1. is YES. Their rationale was a simple and effective business strategy. An approach that sacrificed proprietary control in exchange for market penetration. To illustrate that strategy:- The oil industry presented the automobile manufacturers with a simple but effective common denominator, the petrol pump with its standardised ...


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