44

When calling the mouse driver interrupt with AX = 0, it returns 0xFFFF in AX if a mouse driver is installed. So if it is installed, the code with INC AX will increment AX back to 0 and then it will just reset the mouse driver a second time. It is very typical that interfaces that use software interrupts give you back a status code in AL or AX, so this is no ...


27

Calling an interrupt service is more like invoking a system call than it is like writing to a memory-mapped register. That is, when you invoke a software interrupt, there is no guarantee that the register values will be the same that they have been before the interrupt call. In fact, most of the time, they will not be, unless the interrupt service routine ...


27

Or was the clock maintained in software, and based off of something like the 18.2 Hz system timer interrupt? This is exactly how time was tracked; you can see the implementation of the timer tick handler in the IBM PC Technical Reference, page A-77. It updates a counter, stored in memory as a double word at 0x0040:0x006C, and checks for elapsing days, ...


25

On the BBC Micro, the byte after the BRK instruction held the error number, followed by the error message string terminated with 0x0D. CALLing the address of the BRK instruction would cause an error to be raised. Update with example, as a runnable BBC BASIC program: 10 DIM b% 32 20 ?b%=0: REM BRK 30 ?(b%+1)=42: REM Error number 42 40 $(b%+2)="StackExchange"...


21

It seems the diagrams are not accurate. I wrote a test program that traces INT1 invocations (and delays execution during INT1 to increase the chance of getting hit by timer interrupts) while executing the following machine language fragment: pushf mov ax, 300h ; 100h = TF; 200h = IF push ax popf ; This instruction sets the trace flag mov ...


20

Without issuing a CLI, no further interrupts can occur (until EOI, at least, where flags are restored by the RTI instruction). As this is a raster interrupt, you need to acknowledge that as well for another one to happen, which the seemingly benign $D019 manipulation achieves earlier in the interrupt handler, cf. the linked FLI routine. In this specific ...


20

was there a risk that the user program had left the stack pointer close to wrapping round, so that the interrupt itself (which pushes three words onto the stack) or the code running in the interrupt would overwrite part of the stack segment? Yep. The 8086 required space to put 6 bytes on the stack: The processor status The current instruction pointer The ...


20

The BRK instruction on the MOS 6502 seems to be one of the more ill-documented features of the processor. [...] Given the lack of documentation about this It is documented quite well and in depth in the corresponding MCS 6500 Microcomputer Family Programming Manual of January 1976 (and all follow ups). Check page 144 and after for description, reasoning ...


16

In a 100% compatible PC, NMI is used only to communicate unrecoverable errors — normally a RAM parity failure, but possibly something else, which should reveal itself via one of the system control ports, specifically you should check: Port A: b4: watchdog timer status; Port B: b6: channel check failure (i.e. a bus failure, likely a peripheral device); b7:...


13

An I/O device will monitor IORQ, M1, and the address bus to determine whether to respond to an I/O cycle. As soon as the CPU negates IORQ the I/O device will stop responding. This ensures the CPU is always in control of how long an I/O device is driving the bus. If an I/O device continued to drive the data bus after IORQ was negated then it would be a ...


13

We need to distinguish here between the "stack," which is a data structure in the imagination of the programmer, and what the CPU does with stack registers and the memory pointed to by them, which is a mechanical process. When the CPU pushes a value on the stack it simply changes the values in the stack pointer register and certain memory locations; whether ...


13

Or was the clock maintained in software, and based off of something like the 18.2 Hz system timer interrupt? Exactly that. It is a 32 bit counter incremented by one every time INT 8 is triggered by the 8253 counter #3 (via INT 0). If the latter, was it common to lose clock accuracy if the timer rate was changed by a running program? That depends much on ...


12

The First Part Done bit is used to signal whether a specific part of an instruction (the "first part") is done already or not. It is only set on instructions like ILDB ("Increment and load byte") and ILDW ("Increment and load word") that address a pointer to a byte/word in memory, increment that pointer, and then fetch the byte or word that is referenced ...


12

You're correct; the only interrupts on offer in a Vic-20 are those from a VIA — they're plain old 6522s in the Vic-20, not 6526s. The original VIC chip exposes the current scan line via a couple of registers so instead you'd perform a busy loop until it got to the number you wanted, then cue the VIA. I'm not a C64 expert but besides the lack of hardware ...


12

As indicated by e.g. this description of the Phoenix BIOS, possible NMI sources are Memory parity errors x87 Coprocessor errors I/O card NMI (for whatever reason the I/O card decides to invoke it) DMA bus time-out errors (AT only) Additionally, the Programmable Interrupt Timer (PIT; 8253 or 8254) could generate an NMI using a watchdog and possibly also on ...


12

The SOS operating system written for the Apple /// used BRK for operating system calls. The byte following the BRK holds the OS function number. Of course, the two bytes after that are also used as inline data, so you can argue that it's not a true example of BRK with a signature byte. Still, it's an example of "real world" code using inline data after a ...


12

IM 0 is the backwards-compatibility mode with the i8080 CPU. You have to use some external circuit to provide desired RST 0..38h instruction. RST 0 is effectively the same as RESET, RST 38h is the same as IM 1 mode provides. All the other RST addresses have their own meaning in the ZX Spectrum ROM (see): RST 00h is RESET RST 08h is ERROR RST 10h is PRINT A ...


11

Yes, games like Rescue Raiders and Silent Service used interrupts to queue music and sound effects while other things were happening on the screen. Perhaps the best example of the technique is Skyfox, which had music playing during the frenetic dogfight action. The option to have simultaneous graphics and great sound without cycle-counting was one of the ...


11

The 8254 system timer calls interrupt 08 at regular intervals (18.2 times per second by default), and the latter calls interrupt 1C which is the one you should hook into. You hook into this in the standard DOS way: store the current address at vector 1C, place your routine's address there, and make sure you chain to the previous address from your routine. ...


11

The 0xDD does not allow an interrupt to happen after it's been fetched, no matter what comes next in the instruction stream. As Wayne Conrad pointed out, otherwise the CPU would have to time travel into the future to find out what instruction is going to get fetched.


10

You might want to consult the chapter for 'Interrupt Response' of the CPU manual (Chapter 8 on p.55 of the 1976 issue) and 'Interrupt Servicing' from the PIO manual (Chapter 6 on p.15 of the 1977 issue). In general the Z80 supports 3 different interrupt modes: Mode 0 - like 8080, here the interrupting device must place an instruction on the bus - usually ...


10

The 6502 is designed to be used in systems with devices that may need to cause an interrupt. The way this is accommodated is by having each device use an open-collector/open-drain output to drive the /IRQ pin, which is passively pulled up with a resistor. If any device wants the /IRQ pin low, it will be low. Only if no device wants it low will it be high. ...


10

On the IBM PCJr, the NMI was used by the keyboard device to signal the CPU. (Source: “The Peter Norton Programmer’s Guide to the IBM PC”, chapter 3, under “Changing Interrupt Vectors” while discussing CLI)


10

My two cents: I have written a lot of code with interrupts, and failed many times. Interrupts are very difficult to debug because they are asynchronous, you cannot easily enforce the same conditions again and again and you are fighting against race conditions and a lot of "background" operations. The main problem, in my opinion, was that Woz had to program ...


9

Interrupt Mode 2 is not a ZX Spectrum feature, it's a feature of the Zilog Z80 CPU itself. Per Raffzahn@'s comment, the answer to your question kinda depends on what kind of threading you're talking about. There are generally two levels of abstraction when it comes to multithreading, and two meanings of the term. First is the hardware level Simultaneous ...


9

Not simultaneously, as it only has one CPU, but it has a 50 Hz timer interrupt, so it can do time sharing processing, provided that programs are well behaved, as there is no memory protection and no supervisor mode in the CPU. As a proof of concept, I've written a small task scheduler and tasks that are executed in a time sharing fashion (with a 20ms ...


9

To save space and execution time (and partly of necessity, cf. below), interrupt handlers are typically set up for the context they are used in with assumptions on expected system interrupt sources. If you were to set up a context in which you might be receiving interrupts from both the VIC (maybe raster or sprite collision interrupt) and a CIA (maybe a ...


9

but I can't find any explicit documentation. The documentation for the Z80 behaviour is in its manual. For the way the CPC hardware handles it, you may need to see these circuits. It may, for example hold an IRQ until it is accepted. but what happens in the case of the prefix? Is the interrupt acknowledged after the next instruction has been executed? The ...


8

As I know it probably do not any effect on IRQ routine. Or do it? No, it does not. Well, it does, but that depends. Before entering an interrupt routine the interrupt disable flag (I) is set, preventing the CPU from accepting other interrupts so it can setup the environment needed to do its job without being interrupted again. Basically an implied SEI, ...


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