24

On the BBC Micro, the byte after the BRK instruction held the error number, followed by the error message string terminated with 0x0D. CALLing the address of the BRK instruction would cause an error to be raised. Update with example, as a runnable BBC BASIC program: 10 DIM b% 32 20 ?b%=0: REM BRK 30 ?(b%+1)=42: REM Error number 42 40 $(b%+2)="StackExchange"...


20

Without issuing a CLI, no further interrupts can occur (until EOI, at least, where flags are restored by the RTI instruction). As this is a raster interrupt, you need to acknowledge that as well for another one to happen, which the seemingly benign $D019 manipulation achieves earlier in the interrupt handler, cf. the linked FLI routine. In this specific ...


20

The BRK instruction on the MOS 6502 seems to be one of the more ill-documented features of the processor. [...] Given the lack of documentation about this It is documented quite well and in depth in the corresponding MCS 6500 Microcomputer Family Programming Manual of January 1976 (and all follow ups). Check page 144 and after for description, reasoning ...


20

It seems the diagrams are not accurate. I wrote a test program that traces INT1 invocations (and delays execution during INT1 to increase the chance of getting hit by timer interrupts) while executing the following machine language fragment: pushf mov ax, 300h ; 100h = TF; 200h = IF push ax popf ; This instruction sets the trace flag mov ...


16

In a 100% compatible PC, NMI is used only to communicate unrecoverable errors — normally a RAM parity failure, but possibly something else, which should reveal itself via one of the system control ports, specifically you should check: Port A: b4: watchdog timer status; Port B: b6: channel check failure (i.e. a bus failure, likely a peripheral device); b7:...


16

was there a risk that the user program had left the stack pointer close to wrapping round, so that the interrupt itself (which pushes three words onto the stack) or the code running in the interrupt would overwrite part of the stack segment? Yep. The 8086 required space to put 6 bytes on the stack: The processor status The current instruction pointer The ...


12

You're correct; the only interrupts on offer in a Vic-20 are those from a VIA — they're plain old 6522s in the Vic-20, not 6526s. The original VIC chip exposes the current scan line via a couple of registers so instead you'd perform a busy loop until it got to the number you wanted, then cue the VIA. I'm not a C64 expert but besides the lack of hardware ...


12

As indicated by e.g. this description of the Phoenix BIOS, possible NMI sources are Memory parity errors x87 Coprocessor errors I/O card NMI (for whatever reason the I/O card decides to invoke it) DMA bus time-out errors (AT only) Additionally, the Programmable Interrupt Timer (PIT; 8253 or 8254) could generate an NMI using a watchdog and possibly also on ...


11

The First Part Done bit is used to signal whether a specific part of an instruction (the "first part") is done already or not. It is only set on instructions like ILDB ("Increment and load byte") and ILDW ("Increment and load word") that address a pointer to a byte/word in memory, increment that pointer, and then fetch the byte or word that is referenced ...


11

An I/O device will monitor IORQ, M1, and the address bus to determine whether to respond to an I/O cycle. As soon as the CPU negates IORQ the I/O device will stop responding. This ensures the CPU is always in control of how long an I/O device is driving the bus. If an I/O device continued to drive the data bus after IORQ was negated then it would be a ...


10

The 8254 system timer calls interrupt 08 at regular intervals (18.2 times per second by default), and the latter calls interrupt 1C which is the one you should hook into. You hook into this in the standard DOS way: store the current address at vector 1C, place your routine's address there, and make sure you chain to the previous address from your routine. ...


10

You might want to consult the chapter for 'Interrupt Response' of the CPU manual (Chapter 8 on p.55 of the 1976 issue) and 'Interrupt Servicing' from the PIO manual (Chapter 6 on p.15 of the 1977 issue). In general the Z80 supports 3 different interrupt modes: Mode 0 - like 8080, here the interrupting device must place an instruction on the bus - usually ...


10

On the IBM PCJr, the NMI was used by the keyboard device to signal the CPU. (Source: “The Peter Norton Programmer’s Guide to the IBM PC”, chapter 3, under “Changing Interrupt Vectors” while discussing CLI)


10

We need to distinguish here between the "stack," which is a data structure in the imagination of the programmer, and what the CPU does with stack registers and the memory pointed to by them, which is a mechanical process. When the CPU pushes a value on the stack it simply changes the values in the stack pointer register and certain memory locations; whether ...


10

The SOS operating system written for the Apple /// used BRK for operating system calls. The byte following the BRK holds the OS function number. Of course, the two bytes after that are also used as inline data, so you can argue that it's not a true example of BRK with a signature byte. Still, it's an example of "real world" code using inline data after a ...


9

The 6502 is designed to be used in systems with devices that may need to cause an interrupt. The way this is accommodated is by having each device use an open-collector/open-drain output to drive the /IRQ pin, which is passively pulled up with a resistor. If any device wants the /IRQ pin low, it will be low. Only if no device wants it low will it be high. ...


9

Yes, games like Rescue Raiders and Silent Service used interrupts to queue music and sound effects while other things were happening on the screen. Perhaps the best example of the technique is Skyfox, which had music playing during the frenetic dogfight action. The option to have simultaneous graphics and great sound without cycle-counting was one of the ...


8

As I know it probably do not any effect on IRQ routine. Or do it? No, it does not. Well, it does, but that depends. Before entering an interrupt routine the interrupt disable flag (I) is set, preventing the CPU from accepting other interrupts so it can setup the environment needed to do its job without being interrupted again. Basically an implied SEI, ...


7

I have looked this video - Altair 8800 - Interrupt Acknowledge Cycle and have few questions (I have read wikipedia Intel 8080 article, Altair 8800 Operator's manual, Charles Petzold "Code" and few article on the internet, like this and didn't found answer yet): Maybe to start with the obvious: Not every device needs to be interrupt driven. Altair 8800 ...


6

Like with any other misbehaving bus user - it crashes one way or another. Such a behaviour is just not valid, thus there is no way to recover (in fact, it's even hard to detect it anyway). For example, consider the case where the ISR routine has an OUT instruction. This makes the CPU attempt to drive the databus which the misbehaving IO device is still ...


6

1 I/O port <> 1 hardware device 1 RST vector <> 1 interrupt from one device You have read the datasheet under false assumptions. There is no such thing as a 1:1 correlation between these concepts. Actually, I/O devices that hold only one single I/O port are pretty rare. A typical floppy controller, for example, the WD1772, has four registers (...


6

The original IBM 5150 Personal Computer (the IBM PC) connected the Non-Maskable Interrupt to the I/O Check signal, which could be driven by an add-in card, or by the on-board memory. If the systems memory detected a parity error, it would trigger a NMI, and the systems software would halt the machine and display an on screen error. You can read about this in ...


5

The 6502 only has a single IRQ line which is used by any device connected to it. In the C64, we have the CIA#1 and the VIC-II connected to IRQ. The CPU reacts on a signalled IRQ only if its interrupt flag is cleared. When starting to service an IRQ, the interrupt flag is set automatically and will stay set until either the end of the ISR (Interrupt service ...


5

The VIC keeps the CPU interrupt line activated until the cause for the interrupt is acknowledged, so if you don't tell the VIC which of the interrupts are now handled it won't release the CPU interrupt line and CPU keeps executing the interrupt routine.


5

Wikipedia seems to be wrong here. From the Intersil Manual: DEVICE INTERRUPT GRANT TIMING The current content of the Program Counter, PC, is deposited in location 0000 of the memory and the program fetches the instruction from location 0001... That clearly implies to me there is no address stored at 0001. Beyond that, there's not much of a ...


5

Assuming you're not actually going to chain the existing interrupt handler to your own, I think you should end with rti and more besides. A disassembly of the C64 firmware shows that IRQs jump to FF48, which pushes A, X and Y to the stack in that order, loads the value that was at the top of the stack and if it does not have $10 set — i.e. if the triggering ...


5

The Compute's Gazette Disk menu used raster tricks to set the background color on a per-line basis, and the Demon Attack cartridge used a black character color as the "apparent" background while it changed the background color every scan line to achieve colorful demons like the Atari 2600 version. My recollection is that the Compute's Gazette menu did not ...


5

Unless your IRQ routine was large you'd expect enough space to be left on the stack. You could swap to your own dedicated stack before carrying on. Most of the time you would usually just be copying data over from the interrupting device anyway (or setting the next DMA buffer). Terminate and stay resident code (e.g. SideKick) that hooked keyboard vectors ...


4

Manassehkatz is correct about the bus. All components can see all bus activity. So each picks for itself which bus cycles to respond to; ordinarily IO accesses to a particular address or range of addresses. The 8080 has a very direct interrupt system — it'll read an instruction off the bus and execute it. In practice it's easier to make these single byte ...


4

Here's the equivalent diagram from the Z84C00 datasheet (which applies to NMOS Z80s as well as the later CMOS versions), which is a little clearer. The first thing to notice is that it's actually different: the diagram you show has the bus being released by the device before the CPU deasserts ~IORQ. This is actually wrong: here the timing is explicit, and ...


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