8

To save space and execution time (and partly of necessity, cf. below), interrupt handlers are typically set up for the context they are used in with assumptions on expected system interrupt sources. If you were to set up a context in which you might be receiving interrupts from both the VIC (maybe raster or sprite collision interrupt) and a CIA (maybe a ...


8

Based on my findings above, it seems that there is no need to identify the IRQ source in interrupt handlers, or at least it is not a regular practice. Why? Because there are no unknown/unexpected interrupts? The C64 is a rather simple machine, originally developed as a game console. Later usage is still much like one. C64 software assumes to be loaded as ...


8

In the original PC/AT Architecture, the FPU exception signal that should be connected directly to a dedicated input pin on the main CPU and should appear as INT 10h gets re-routed by glue logic to the second IRQ controller so that it appears as IRQ 13 (i.e. INT 75h) instead. Most of the other conflicting vectors are of such a nature that the hardware-defined ...


5

You can actually generate a "spurious interrupt" condition on the Atari ST with its MFP (68901) - Not on purpose, but rather because of a glitch in the Motorola 68901 - If you disable interrupts on the MFP exactly at the point when the CPU starts an IACK cycle (i.e with the last instructions before the /INT), it will not provide a vector, the CPU ...


5

The general principle of what you're doing would seem to be correct. I would add, though, that unless you're doing anything outside the interrupts except spinning, you would need to save and restore processor registers to ensure the interrupt handlers to not mess with that code. In fact, that part, outside the interrupt handlers, is what you'd typically ...


4

My opinion is that I wouldn't rely too much on Z80 daisy-chained interrupts. It was actually invented to "dissolve" the need for the dedicated interrupt controller IC among the ordinary peripheral chips. Besides that only useful feature, everything else is disadvantage: The need for extra logic inside chips, i.e. decoding RETI instruction and ...


1

This answer is an attempt at a “middle of the road” solution: not as flexible as a fully decoded IM2 system with 128 interrupt vectors, but certainly practical enough not to require programmable logic. Routing the IEI/O chain through modules in a general purpose system is not the best idea due to timing constraints and the general Z80-specificity - it’s not ...


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