93

For once, I do have a direct source for a "Why didn't they ...?" question. Eric Isaacson, back in the late '80s and '90s, wrote a commercial assembler for the 8086, called A86. (His homepage still has a section offering it for sale for $50, $52 outside North America, and explaining why it's the best assembler on the market for DOS. You can even download ...


79

There was a 640K limit on the original IBM PC, but it was the result of IBM’s design decisions, and nothing to do with Microsoft: it’s the largest contiguous amount of memory which can be provided without eating into reserved areas of memory. The IBM PC Technical Reference includes a system memory map (page 2-25): which is detailed on subsequent pages: the ...


43

I’m not sure the separate cache was “obviously better” back when the Intel designers were working on the 80486, at least, not to the designers in question. But “better” might not even have been much of a factor. The design history of the cache systems in Motorola and Intel CPUs is quite different, which can explain the different approaches used in the 68040 ...


41

The PDP-10 had 'byte instructions' that could process a sequence of bytes of size 1 to 36 bits. The byte pointer was a word containing an 18-bit word address (and the usual index/indirect indications) plus position and size of the byte within the word. It was common to use 7-bit byte sequences for ASCII text, which gave 5 characters per word and one (...


40

It is not intentionally mirrored, it is just a side effect of making the address decoding hardware for RAM as simple and cheap as possible with a single common 74LS139 chip used for the task, when an 8k area of addresses are reserved for RAM, but only 2k of RAM is present in the 8k area. If you look at the address map, 0x0000 to 0x1FFF is reserved for the ...


35

Memory is allocated statically in Super Mario World. Every RAM location used is hard-coded into the game, although some are re-used by different parts of the code. A full, annotated, and searchable memory map for Super Mario World (archive) with 824 entries in RAM (4949 total) is presented at SMW Central. If you're interested in glitches due to re-used ...


30

What Boot Code? With 16 KiB it was pitched against the Apple II or the Commodore/Tandy/Atari with BASIC, nothing else. Remember that the PC (!) had a the cassette port? That's the intended mass storage for a 16 KiB system :)) The minimum requirement for floppy use was, as you already guessed, 32 KiB. And oh wonder, DOS can be booted on a 32 KiB machine. ...


26

The 8086 used a segmented memory architecture where the linear address was computed from a 16-bit segment number and a 16-bit offset. This greatly complicated things from a programming perspective. I beg to differ. Using segments doesn't 'complicate' things in any way. Sure, it may require a different style of structuring the data used and there are very ...


26

Did anyone ever put that much memory in an Altair, IMSAI or other 8080/Z80 S-100 bus machine? Has been done a lot of times. Remember, S100 has been used all the way thru the 1980s into the 1990s. RAM sizes did pass the basic 64 Ki already before 1980 and went way beyond 2 MiB soon after. Boards were available by all major S100 supporters, including Cromemco,...


25

Sideways ROM (also RAM in later models) was paged into the processor's address space. Sideways memory sat in the address range from $8000 to $BFFF. The BBC Model B had four slots on the motherboard into which EPROMs could be put to occupy this space. One of the slots was reserved for BBC Basic. Expansion boards could be purchased to expand this to 16 ...


24

All of the 68k-based computers (Amiga, Atari ST and Sinclair QL, as well as the classic Macintosh) went to market in a rush. And all of them went to market before the OS (and, thus, the ROMs) were really "finished". The QL initially had an outboard ROM extension that later on had to be replaced with the "final" ROMs (so, the computer had ...


23

It was part of the 68000 system architecture in which all the interrupt vectors are low in the memory map. The first 1024 bytes are reserved for these vectors and if a program / os need to change these, hardcoding into ROM wouldn't work. The vendor (Motorola) had application notes in which on a cold boot or reset, the ROM was mapped low. The idea came from ...


23

The TRS-80 series is Z80 based, and Z80 uses, like all 8080 offspring (*1,3) a separate address space for I/O. It allows easy decoding for I/O. Thus memory address 0000h is different from I/O address 00h. On logical (program) level, access to either address space is selected by the instructions used. Memory instructions always access memory address space ...


22

According to Wikipedia, The unusual architecture of the 99/4 series is documented to be due to the failure of the 9985, an 8-bit processor which was being created specifically for the machine. When it was abandoned, the 16-bit 9900 was selected to replace it, and a great deal of "glue logic" had to be added to fit the processor into the existing design, ...


22

Following up on the @StephenKitt answer: CP/M put BIOS and BDOS code at the top of RAM, and IBM decided to copy that idea. Just like with CP/M systems, the plan was to raise the start of reserved memory from A0000 (640KB) to a higher value once newer chips like the 80286 arrived. This would have worked if end-user programmers like at Lotus obeyed MSFT's ...


21

Stephens Answer already carries most implications, so this is merely an add-on. First to keep in mind is that the 68k was way more in need of a cache than x86 CPUs, as its memory access was in line with execution, while the x86 prefetch buffer used 'free' cycles to read ahead, thus utilizing the memory much better than the 68k could do (*1). Next, it ...


18

Now given that the TMS9900 has a 16 bit databus, it seems to me that they could have put all memory and all periphery on that bus. It would have saved the cost of the multiplexor, and made the computer a good deal faster too. Presumably it would have simplified the routing of the circuit board also. Yes it would - if the computer had been intended to be ...


18

Trust Vice. The information you obtained elsewhere is incorrect. Each line of the BASIC program is preceded by a pointer to the next line. Then, comes the line number. Following this is the tokens that make up the actual BASIC code of the line, and terminated by a null ($00). Then starts the next line (#2) with a pointer to line #3. The end of the BASIC ...


17

Notepad (at least originally) was implemented as a simple wrapper around the Windows EDIT control. EDIT is not really designed to handle large amounts of text -- it stores text in a single block of memory allocated via LocalAlloc (which, at least for 16-bit versions of Windows, means that it can't handle more than 64K of text in a single control, and in ...


17

JSR works how you think — the program counter will head off to 80fa — but the SNES doesn't. The two most common memory mappers both mirror what's at $00xx at $80xx. So when the processor reads from $80fa it gets the same thing as if it read from $00fa. Per the linked article, in a 'HiROM' (i.e. one of the two common types): Banks $80 - $FF can also be ...


17

The XMS specification is still accurate: functions 0x10 and 0x11 provide access to UMBs. However, the specification doesn’t decide where those functions are implemented. On its own, HIMEM.SYS does indeed only provide access to memory above 1MiB, i.e. the HMA (so it also controls the A20 line) and extended memory (which it makes available as XMS). If you only ...


17

As discussed and linked in this thread, Norbert Landsteiner has written a series of blog posts on masswerk.at that cover Commodore BASIC V2 internal program and data representation in detail and giving some code to do renumbering of BASIC programs and other interesting things. (He does this on a PET with v2 ROM; C64 is substantially similar but see my ...


16

The 6510 CPU used in the Commodore 64 has an additional built-in general purpose I/O port compared to the original 6502 CPU. Address $0000 controls the direction for each of the bits of this I/O port, address $0001 can be used to read the voltage level of the corresponding pin for inputs, or set the voltage level of this pin for output. In the Commodore 64, ...


16

The C64 BASIC ROM lives at $A000, the KERNEL ROM lives at $E000, but these ROMs also have RAM wired in 'parallel' Under normal operation this RAM is unused but you can use the LORAM/HIRAM bits to enable or disable the ROMS and switch in the equivalent RAM memory. One fun trick is to write a quick basic program to PEEK all the addresses from $A000 to $FFFF ...


16

A Z80 will always do a refresh cycle during T3/T4 of an M1 cycle. Disabling is not possible. During a refresh cycle the /RFSH signal will be active for both cycles, signaling a valid refresh address, while /MREQ is active during the second half of T3 and the first half of T4. Neither /RD nor /WR will be active during T3/T4. Thus a refresh cycle is never a ...


16

Amstrad used an off-the-shelf component, and did the best they could. For generating video addresses, sync timing, etc, Amstrad used the 6845 CRTC, which was originally designed for text displays. In particular it is designed for a linear text area, looking up character graphics from a font ROM, so e.g. if you’ve set up a 40-column display with 8px ...


16

If you count Altair clones, yes. For the original Altair 8080, quite possibly (if the PSU was capable of powering eight of the IMSAI memory boards along with the CPU and I/O boards) and for the Altair 8080b, almost certainly (it had a more powerful PSU). IMSAI did pretty much exactly what you suggested in your question, but a year earlier than the date you ...


15

"Incomplete decoding" means that the address decoder only pays attention to a few of the address lines: the high bits indicating the PPU chip and the three low bits selecting a register on that chip. The purpose of doing this is to simplify things: by ignoring most of the address lines, the PPU chip needs fewer pins, while a three-bit address decoder is a ...


15

The minimal version of IBM PC, also known as cassette version, was shipped with 40KB ROM and 16KB RAM as outlined in IBM 5150 Technical Reference (SECTION I. HARDWARE OVERVIEW in the reference): The System Board is a large board which fits horizontally in the base of the System Unit and includes the microprocessor, 40KB ROM and 16KB memory. The memory ...


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