95 votes
Accepted

Why didn't the 8086 use linear addressing?

For once, I do have a direct source for a "Why didn't they ...?" question. Eric Isaacson, back in the late '80s and '90s, wrote a commercial assembler for the 8086, called A86. (His homepage still ...
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  • 5,690
79 votes
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Who set the 640K limit?

There was a 640K limit on the original IBM PC, but it was the result of IBM’s design decisions, and nothing to do with Microsoft: it’s the largest contiguous amount of memory which can be provided ...
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43 votes
Accepted

Why did Intel abandon unified CPU cache?

I’m not sure the separate cache was “obviously better” back when the Intel designers were working on the 80486, at least, not to the designers in question. But “better” might not even have been much ...
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43 votes
Accepted

Did any computer use a 7-bit byte?

The PDP-10 had 'byte instructions' that could process a sequence of bytes of size 1 to 36 bits. The byte pointer was a word containing an 18-bit word address (and the usual index/indirect indications)...
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40 votes
Accepted

What is the purpose of mirrored memory regions in NES's CPU memory map?

It is not intentionally mirrored, it is just a side effect of making the address decoding hardware for RAM as simple and cheap as possible with a single common 74LS139 chip used for the task, when an ...
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35 votes

How is memory allocated in Super Mario World?

Memory is allocated statically in Super Mario World. Every RAM location used is hard-coded into the game, although some are re-used by different parts of the code. A full, annotated, and searchable ...
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  • 351
35 votes
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What were the actual memory model definitions in MS-DOS?

The memory model all had to do with how much code and/or data your program was using. First some background. The 8086(1) was based on earlier Intel chips where their address space was strictly 64K and ...
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  • 2,386
30 votes
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How did an IBM 5150 with 16KB RAM work?

What Boot Code? With 16 KiB it was pitched against the Apple II or the Commodore/Tandy/Atari with BASIC, nothing else. Remember that the PC (!) had a the cassette port? That's the intended mass ...
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30 votes
Accepted

How did old computers address far more than 64K of memory despite only having a 16 bit address bus?

I don't know details of the Sharp PC-G830 specifically but the technique used to address more than 64K with a 16-bit address bus is called "bank switching". This involves setting up some ...
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  • 1,614
26 votes
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How did the Sideways address space work?

Sideways ROM (also RAM in later models) was paged into the processor's address space. Sideways memory sat in the address range from $8000 to $BFFF. The BBC Model B had four slots on the motherboard ...
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  • 7,571
26 votes

Why didn't the 8086 use linear addressing?

The 8086 used a segmented memory architecture where the linear address was computed from a 16-bit segment number and a 16-bit offset. This greatly complicated things from a programming perspective. I ...
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  • 166k
26 votes
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Did anyone ever put half a megabyte of memory in an Altair?

Did anyone ever put that much memory in an Altair, IMSAI or other 8080/Z80 S-100 bus machine? Has been done a lot of times. Remember, S100 has been used all the way thru the 1980s into the 1990s. RAM ...
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24 votes

Why is the Amiga ROM at a high memory location, and RAM in low memory?

All of the 68k-based computers (Amiga, Atari ST and Sinclair QL, as well as the classic Macintosh) went to market in a rush. And all of them went to market before the OS (and, thus, the ROMs) were ...
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23 votes
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Why is the Amiga ROM at a high memory location, and RAM in low memory?

It was part of the 68000 system architecture in which all the interrupt vectors are low in the memory map. The first 1024 bytes are reserved for these vectors and if a program / os need to change ...
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  • 358
23 votes
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What are the "ports" used via IN/OUT, vs. the PEEK/POKE address space?

The TRS-80 series is Z80 based, and Z80 uses, like all 8080 offspring (*1,3) a separate address space for I/O. It allows easy decoding for I/O. Thus memory address 0000h is different from I/O ...
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22 votes

Why did the TI-99/4 have two databuses?

According to Wikipedia, The unusual architecture of the 99/4 series is documented to be due to the failure of the 9985, an 8-bit processor which was being created specifically for the machine. When ...
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22 votes

Who set the 640K limit?

Following up on the @StephenKitt answer: CP/M put BIOS and BDOS code at the top of RAM, and IBM decided to copy that idea. Just like with CP/M systems, the plan was to raise the start of reserved ...
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  • 500
21 votes

Why did Intel abandon unified CPU cache?

Stephens Answer already carries most implications, so this is merely an add-on. First to keep in mind is that the 68k was way more in need of a cache than x86 CPUs, as its memory access was in line ...
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  • 166k
18 votes
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How does JSR actually work on the 65c816 CPU for the SNES (Super Nintendo)?

JSR works how you think — the program counter will head off to 80fa — but the SNES doesn't. The two most common memory mappers both mirror what's at $00xx at $80xx. So when the processor reads from $...
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18 votes

Why did the TI-99/4 have two databuses?

Now given that the TMS9900 has a 16 bit databus, it seems to me that they could have put all memory and all periphery on that bus. It would have saved the cost of the multiplexor, and made the ...
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  • 166k
18 votes
Accepted

How was a line of Commodore 64 BASIC code stored in its memory?

Trust Vice. The information you obtained elsewhere is incorrect. Each line of the BASIC program is preceded by a pointer to the next line. Then, comes the line number. Following this is the tokens ...
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17 votes
Accepted

How does Notepad store text files in memory?

Notepad (at least originally) was implemented as a simple wrapper around the Windows EDIT control. EDIT is not really designed to handle large amounts of text -- it stores text in a single block of ...
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17 votes
Accepted

What manages Upper Memory Blocks (UMBs) in MS-DOS?

The XMS specification is still accurate: functions 0x10 and 0x11 provide access to UMBs. However, the specification doesn’t decide where those functions are implemented. On its own, HIMEM.SYS does ...
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17 votes

How was a line of Commodore 64 BASIC code stored in its memory?

As discussed and linked in this thread, Norbert Landsteiner has written a series of blog posts on masswerk.at that cover Commodore BASIC V2 internal program and data representation in detail and ...
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17 votes

What were the actual memory model definitions in MS-DOS?

The memory models were defined by compilers for high-level languages, and were reasonably standard between Microsoft, Borland and Watcom. The Small, Medium, Compact and Large models appear to have ...
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  • 5,690
16 votes
Accepted

How does the Commodore 64 address more than 64 kilobytes of memory?

The 6510 CPU used in the Commodore 64 has an additional built-in general purpose I/O port compared to the original 6502 CPU. Address $0000 controls the direction for each of the bits of this I/O port, ...
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16 votes

How does the Commodore 64 address more than 64 kilobytes of memory?

The C64 BASIC ROM lives at $A000, the KERNEL ROM lives at $E000, but these ROMs also have RAM wired in 'parallel' Under normal operation this RAM is unused but you can use the LORAM/HIRAM bits to ...
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  • 8,416
16 votes
Accepted

Disable memory refresh on Z80

A Z80 will always do a refresh cycle during T3/T4 of an M1 cycle. Disabling is not possible. During a refresh cycle the /RFSH signal will be active for both cycles, signaling a valid refresh address, ...
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  • 166k
16 votes
Accepted

Why did the Amstrad CPC use a nonlinear screen memory layout?

Amstrad used an off-the-shelf component, and did the best they could. For generating video addresses, sync timing, etc, Amstrad used the 6845 CRTC, which was originally designed for text displays. In ...
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