77

For once, I do have a direct source for a "Why didn't they ...?" question. Eric Isaacson, back in the late '80s and '90s, wrote a commercial assembler for the 8086, called A86. (His homepage still has a section offering it for sale for $50, $52 outside North America, and explaining why it's the best assembler on the market for DOS. You can even download ...


61

There was a 640K limit on the original IBM PC, but it was the result of IBM’s design decisions, and nothing to do with Microsoft: it’s the largest contiguous amount of memory which can be provided without eating into reserved areas of memory. The IBM PC Technical Reference includes a system memory map (page 2-25): which is detailed on subsequent pages: the ...


45

No, it didn't. MS-DOS never bothered to zero out allocated memory, as there was no security reason to do so like there is in a multi-user operating system. It was up to the C runtime startup code to zero out the BSS segment. For example, from the Borland C++ 3.1 startup code: ; Reset uninitialized data area xor ax, ax ...


42

I’m not sure the separate cache was “obviously better” back when the Intel designers were working on the 80486, at least, not to the designers in question. But “better” might not even have been much of a factor. The design history of the cache systems in Motorola and Intel CPUs is quite different, which can explain the different approaches used in the 68040 ...


26

The 8086 used a segmented memory architecture where the linear address was computed from a 16-bit segment number and a 16-bit offset. This greatly complicated things from a programming perspective. I beg to differ. Using segments doesn't 'complicate' things in any way. Sure, it may require a different style of structuring the data used and there are very ...


23

Sideways ROM (also RAM in later models) was paged into the processor's address space. Sideways memory sat in the address range from $8000 to $BFFF. The BBC Model B had four slots on the motherboard into which EPROMs could be put to occupy this space. One of the slots was reserved for BBC Basic. Expansion boards could be purchased to expand this to 16 ...


22

According to Wikipedia, The unusual architecture of the 99/4 series is documented to be due to the failure of the 9985, an 8-bit processor which was being created specifically for the machine. When it was abandoned, the 16-bit 9900 was selected to replace it, and a great deal of "glue logic" had to be added to fit the processor into the existing design, ...


21

Stephens Answer already carries most implications, so this is merely an add-on. First to keep in mind is that the 68k was way more in need of a cache than x86 CPUs, as its memory access was in line with execution, while the x86 prefetch buffer used 'free' cycles to read ahead, thus utilizing the memory much better than the 68k could do (*1). Next, it ...


20

All of the 68k-based computers (Amiga, Atari ST and Sinclair QL, as well as the classic Macintosh) went to market in a rush. And all of them went to market before the OS (and, thus, the ROMs) were really "finished". The QL initially had an outboard ROM extension that later on had to be replaced with the "final" ROMs (so, the computer had to be sent back to ...


17

Notepad (at least originally) was implemented as a simple wrapper around the Windows EDIT control. EDIT is not really designed to handle large amounts of text -- it stores text in a single block of memory allocated via LocalAlloc (which, at least for 16-bit versions of Windows, means that it can't handle more than 64K of text in a single control, and in ...


16

Now given that the TMS9900 has a 16 bit databus, it seems to me that they could have put all memory and all periphery on that bus. It would have saved the cost of the multiplexor, and made the computer a good deal faster too. Presumably it would have simplified the routing of the circuit board also. Yes it would - if the computer had been intended to be ...


16

Following up on the @StephenKitt answer: CP/M put BIOS and BDOS code at the top of RAM, and IBM decided to copy that idea. Just like with CP/M systems, the plan was to raise the start of reserved memory from A0000 (640KB) to a higher value once newer chips like the 80286 arrived. This would have worked if end-user programmers like at Lotus obeyed MSFT's ...


15

The 6510 CPU used in the Commodore 64 has an additional built-in general purpose I/O port compared to the original 6502 CPU. Address $0000 controls the direction for each of the bits of this I/O port, address $0001 can be used to read the voltage level of the corresponding pin for inputs, or set the voltage level of this pin for output. In the Commodore 64, ...


15

It was part of the 68000 system architecture in which all the interrupt vectors are low in the memory map. The first 1024 bytes are reserved for these vectors and if a program / os need to change these, hardcoding into ROM wouldn't work. The vendor (Motorola) had application notes in which on a cold boot or reset, the ROM was mapped low. The idea came ...


13

The idea is as old as memory-mapped display hardware is. After all, memory bandwidth was for most of the time the limiting factor. Every character based text screen only updates what needs to be changed and similar each and every game - maybe with an exception of the Atari VCS 'Racing the Beam' :) Similar double buffering. As soon as a machine supports ...


12

I am pretty sure the Intel engineers just weren't there, yet. And they were pressed by the market to push out a 16-bit CPU before all the others did to keep the market share they had already lost big time to small Zilog. (I am pretty sure that the design of the 8086 was much more driven by marketing pressure TTM and compatibility constraints than engineering ...


12

Are there any areas of the 64k RAM which are permanently unusable by anything, whether by the built-in monitor ROM or user programs? No. All is usable. After all, Woz did it. He never wasted a single gate, even less RAM. Looking at $C000-C0FF, this is the "softswitch" area, and as far as I can determine, the 256 bytes of RAM that occupies this space may ...


12

The simplest way to do that is extending your address bus by at least one bit and have a latch (like, for example, a 74279 TTL latch) to store these bits. Then put in some address decoding to memory-(or i/o-) map this latch as a register allowing you to store arbitrary values in there. Whatever you put into this latch then will determine which area of ...


12

"Incomplete decoding" means that the address decoder only pays attention to a few of the address lines: the high bits indicating the PPU chip and the three low bits selecting a register on that chip. The purpose of doing this is to simplify things: by ignoring most of the address lines, the PPU chip needs fewer pins, while a three-bit address decoder is a ...


12

It's part of the BASIC interpreter loop. It reads one byte of the tokenized BASIC program, setting zero flag if it's a colon or a zero byte and clearing the carry if it's a number. You can see it used in the main part of the interpreter loop at address C6B5. I'm not sure why this routine was placed in zero page. It's a cycle (or rarely two) faster to use ...


12

The C64 BASIC ROM lives at $A000, the KERNEL ROM lives at $E000, but these ROMs also have RAM wired in 'parallel' Under normal operation this RAM is unused but you can use the LORAM/HIRAM bits to enable or disable the ROMS and switch in the equivalent RAM memory. One fun trick is to write a quick basic program to PEEK all the addresses from $A000 to $FFFF ...


12

Since my interpretation of the question differs from other answers posted, I think the primary topic is inter-frame video compression. It's about historical precedents for a pipeline that starts with the complete contents of frame n and frame n+1 in some representation, determines the differences between them, and communicates only the differences to a third ...


11

If bit 0 of location 842 is set then the keyboard scanning routine immediately returns 0x9B which is the code indicating the ENTER key has been pressed. In short, a surprisingly literal effect. The keyboard scan is part of the "OS" ROM built into the machine. There's a source listing I'll excerpt from: Atari 800 ROM OS Source Listing ICAX1Z is a zero ...


11

Just to expand a bit, a cheap address decoder might not take all the address bits and decode them. For a 8 bit processor a simple address decoding scheme might use a 74LS138 to decode the high address bits (A15..A13) into 8K chunks of memory. An alternative might be to use the high bit (A15) as an enable signal (connected to E1 on the 138) and wired to the ...


11

As a personal project I had the idea to create a custom cartridge for my Commodore 64 and use an ATmega 1284p microcontroller to emulate eproms and/or custom chips. I doubt that this will work! The reason is simply the time needed by the microcontroller to react on a signal change: As far as I know, you have about 0.25µs to react on some edge on the C64 ...


9

Calling it a "memory range" is incorrect - and possibly what is leading you astray. The entire range 0000-FFFF is called the "address range" of the CPU - you can write a CPU instruction (or three) that can access a bit, byte or word at any of those addresses. What the hardware does with that access depends on what hardware is "at" that address. The first ...


9

There are many solutions to your problem. use a latch as suggested by tofro. extend this to a full register. This register provides the most significant bits of your extended addressbus. build a minimal MMU yourself by adding the content of a register to the 6502 address (using an adder). use a 6510 instead of a 6502. This processor is used in a Commodore ...


9

[W]hy are some soft switches only activated when written to? Simply because they have been added later. To be exact with the introduction of the IIe/IIc. Originally all Apple II soft switches (including the Language Card) did work just by address selection. Direction was ignored. Usually writes were used, as they do not destroy any register content. Only ...


9

Yes, all 64kb of RAM is accessible. But you ask an interesting question, if we change one letter. ; - ) Address space and device mapping You asked about RAM, but how is RAM read? The CPU puts a 16-bit address on the address bus, puts the R/W' line in the desired state, and then expects a value on the 8-bit data bus within a certain time. What sends the ...


9

Well, original PMD85 was greyscale, so SECAM does not come into the picture (pun intended). The lower 6 bits display as pixels, and these are stored back-to-front. The upper two bits encode an attribute - originally flash (bit 7) and low intensity (bit 6), but in PMD 85-3 this was reinterpreted as 4 level greyscale, or these 4 colours if using an RGB output:...


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