47

No, it didn't. MS-DOS never bothered to zero out allocated memory, as there was no security reason to do so like there is in a multi-user operating system. It was up to the C runtime startup code to zero out the BSS segment. For example, from the Borland C++ 3.1 startup code: ; Reset uninitialized data area xor ax, ax ...


36

The PDP-10 had 'byte instructions' that could process a sequence of bytes of size 1 to 36 bits. The byte pointer was a word containing an 18-bit word address (and the usual index/indirect indications) plus position and size of the byte within the word. It was common to use 7-bit byte sequences for ASCII text, which gave 5 characters per word and one (...


35

Memory is allocated statically in Super Mario World. Every RAM location used is hard-coded into the game, although some are re-used by different parts of the code. A full, annotated, and searchable memory map for Super Mario World (archive) with 824 entries in RAM (4949 total) is presented at SMW Central. If you're interested in glitches due to re-used ...


22

The TRS-80 series is Z80 based, and Z80 uses, like all 8080 offspring (*1,3) a separate address space for I/O. It allows easy decoding for I/O. Thus memory address 0000h is different from I/O address 00h. On logical (program) level, access to either address space is selected by the instructions used. Memory instructions always access memory address space ...


17

Trust Vice. The information you obtained elsewhere is incorrect. Each line of the BASIC program is preceded by a pointer to the next line. Then, comes the line number. Following this is the tokens that make up the actual BASIC code of the line, and terminated by a null ($00). Then starts the next line (#2) with a pointer to line #3. The end of the BASIC ...


16

A Z80 will always do a refresh cycle during T3/T4 of an M1 cycle. Disabling is not possible. During a refresh cycle the /RFSH signal will be active for both cycles, signaling a valid refresh address, while /MREQ is active during the second half of T3 and the first half of T4. Neither /RD nor /WR will be active during T3/T4. Thus a refresh cycle is never a ...


15

Amstrad used an off-the-shelf component, and did the best they could. For generating video addresses, sync timing, etc, Amstrad used the 6845 CRTC, which was originally designed for text displays. In particular it is designed for a linear text area, looking up character graphics from a font ROM, so e.g. if you’ve set up a 40-column display with 8px ...


15

The XMS specification is still accurate: functions 0x10 and 0x11 provide access to UMBs. However, the specification doesn’t decide where those functions are implemented. On its own, HIMEM.SYS does indeed only provide access to memory above 1MiB, i.e. the HMA (so it also controls the A20 line) and extended memory (which it makes available as XMS). If you ...


15

As discussed and linked in this thread, Norbert Landsteiner has written a series of blog posts on masswerk.at that cover Commodore BASIC V2 internal program and data representation in detail and giving some code to do renumbering of BASIC programs and other interesting things. (He does this on a PET with v2 ROM; C64 is substantially similar but see my ...


15

The VT52 text terminal certainly doesn't qualify as a full computer, but it does have a processor running software out of a ROM. The RAM holding the displayed text is 2048 7-bit bytes. The character generator ROM is also 7 bits wide.


13

The Commodore 64 advertises 38911 bytes free for BASIC upon startup. It's a 64kb machine. Non-BASIC programs could use the full 64kb rather than the ~38kb. Therefore using more memory than is available to BASIC was routine. The difference was primarily that BASIC and the rest of the kernel don't need to be present, so if you're not using them then you can ...


10

No, it cannot be disabled, although it can be ignored by the rest of the hardware. Just OR /MREQ with /RFSH negated. Decoding /MREQ along with /RD or /WR is also fine, and you won't need /RFSH. A 74HCT138 3 to 8 decoder can do the job. No, there is no Z80 pin compatible, software compatible processor that allows the user to disable the refresh cycle, but ...


10

The PDP-8 is a 12-bit computer.  As such it has a word and pointer size of 12-bits — meaning it can access 4k words using a single word pointer. Later models added bank switching (KM8E) and 3 extra address lines so that up to 32k words (8x4k) words could be populated, now having 15 address lines.  (Core memory boards, 4k words each, you ...


10

The eXtended Memory Specification (XMS) 2.0 may be found here and the 3.0 version here. The various function calls are invoked by obtaining the driver's entry point via the muxing interrupt (Int 2Fh). XMS allows for accessing both extended (above the 1MB boundary) and high memory areas. XMS works much like the original Windows 16-bit memory management: ...


9

Trying to get more into the specifics of the BBC connection, there is a substantial hint in the user guide: However only 5 bits of the [user] port, and CB1, CB2 are used: This leaves bits 1,3 and 4 available for other uses. Which is backed up by the schematic provided by Simon Inns in the doco for SmallyMouse2; comparing that to the user port's pinout ...


8

I can't speak as to derivatives, but the plain Z80 does not permit you to disable refresh. One refresh cycle will be attached to every operation byte fetched from the instruction stream (with the exception of offsets in IX/IY+d mode). That said, the value placed on the bus during refresh is I:R — the I register is used to populate the top 8 bits, and is ...


7

Problem Here is a picture (to scale) of how memory is being used in units of "pages" (256 bytes) on the Apple 2. 000000001111111111111111 2222222222222222 3 ... ... 9 89ABCDEF0123456789ABCDEF 0123456789ABCDEF 0 ... ... 6 +------------------------+----------------+--------------+ |Basic:::::::::::::::::::|::: HGR | | |Program::...


7

Answers for the Apple II: (Please have a look at this answer to understand the memory layout, and where the areas used by BASIC are placed). 1) Were there any games/software that used memory beyond what was advertised as available to BASIC on the machine? Assuming that "advertised as available to BASIC" means "between $801 and DOS", then yes, machine ...


7

DEC PDP-11 and VAX systems using the Q-Bus had a 'Q-bus map' to map from the bus address space into the physical memory space. This is basically an MMU for devices. On an I/O request from a program, the driver and OS would allocate and initialize map registers, and pass the appropriate bus-virtual address to the device. It's possible for a contiguous bus-...


7

The second-generation Soviet computer Minsk-32 (the series size is 2889 machines, 1968-75, civilian use, one of the rare early mainframes noted for use in Antarctica) used a 37-bit word and 7-bit representation of alphanumeric characters (5 in a word). Yes, the concept of "bytes" is difficult to apply to a similar old computer (which continued the ...


6

For nearly all machines with BASIC, I would expect any non-BASIC programs to use BASIC's workspace. Also, people (inc me) would not allow the OS to get a look-in and use its memory too ;)


6

You'll need to understand something about address decoding to understand what's likely going on in the Game Boy. The Wilson Mines address decoding page is well worth a read, but to summarize, you use logic gates to examine various parts of the address on the address bus and enable and disable different chips (RAM, ROM, I/O devices) based on the address that ...


5

Hardware choice of the IBM engineers, when they put the graphic hardware from address A0000 upward. From a software point of view it was possible to overcome the 640KiB limit if there was memory mapped into the A0000-BFFFF range. On regular PC compatibles it was quite difficult to do but some exotic hardware were able to use that. I personally used a ...


5

Before the 286, x86 CPUs can only access 1MiB, so the only way to use memory beyond 1MiB is to use some form of bank switching. The de facto standard for that is Lotus/Intel/Microsoft EMS, which provides access to expanded memory by switching into a “page frame” (typically located in the UMA, between 640KiB and 1MiB). EMS requires hardware on CPUs before the ...


4

Is it possible to run code directly from ROM [...] by jumping into this region of the address space? Game Code can of course be run from ROM. And most games will do so. If so, why did games generally copy code into RAM before running it? Generally sounds a bit too much here. In fact, as game cartridges range from 4 MiB to 64 MiB (and more), the existing ...


4

During the heyday of the Intel 80386, there were many operating systems that relied on that CPU's virtual 8086 mode to multitask programs that were written for x86 real-mode. By allowing real-mode programs to transparently use the segmented, 20-bit address space that they expected, these Operating Systems provided a fixed-size memory partition to each real-...


4

The Acorn MOS, as deployed in the BBC Micro, offers built-in support for paged ROMs. Paged ROMs have a fixed 16kb window in the address space, and amongst other things may contain filing systems, languages or other programs. A BBC or Electron fitted with more than one paged ROM will therefore have a fixed 16kb ROM window in which the current application ...


4

I don't know the specific details, but in general the mouse uses standard quadrature encoders so for each axis you get two data pins that output movement data. While several ways to decode the quadrature data for each edge to achieve maximum resolution, the hardware uses a simplest possible approach with the PIO chip. Basically a pulse on one pin can be used ...


4

The definition to which you linked is very specific, and you put a further constraint on it that the partitions must all be the same size (the definition to which you linked makes it clear they need not be; the example they give uses four "blocks," which I assume they feel is another word for "partition," of three different sizes). The ...


4

The RSX-11 {D/M/M-PLUS/S} family of operating systems, running on PDP-11 minicomputers, divided real memory into partitions. Partitions were mostly set up at system generation time; you could define partitions in a running system, but that was less common. The RSX-11 family were a reimplementation, on the 16-bit PDP-11, of RSX-15 on the 18-bit PDP-15, so ...


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