New answers tagged memory-layout
2
According to the CPC schematic, the Armstrad uses a gate array to generate video, so we'd need to know how this gate array is programmed for an exact explanation.
But expanding on the comment of supercat, we can do an educated guess:
Assume we have an 8 bit shift register in the gate array, with a tap for bit C0 at the end, a tap for bit C1 in the middle, ...
0
I am not an expert in Amstrad CPC at all, however I can see some regularities, for example:
Not grouping pixel bits in halves (like pixel 0 takes bits 7..4 and pixel 1 takes bits 3..0) allows one to use single shift register, that always shifts by 1 bit.
In mode 2, it shifts 8 times for 8 pixels, in mode 1 it shifts 4 times for 4 pixels, where one pixel is ...
14
Amstrad used an off-the-shelf component, and did the best they could.
For generating video addresses, sync timing, etc, Amstrad used the 6845 CRTC, which was originally designed for text displays. In particular it is designed for a linear text area, looking up character graphics from a font ROM, so e.g. if you’ve set up a 40-column display with 8px ...
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The TRS-80 series is Z80 based, and Z80 uses, like all 8080 offspring (*1,3) a separate address space for I/O. It allows easy decoding for I/O.
Thus memory address 0000h is different from I/O address 00h.
On logical (program) level, access to either address space is selected by the instructions used. Memory instructions always access memory address space ...
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