42

How was microcode implemented in retro processors such as the Z80 or 8080? None of these chips (likewise 6800 and 6502) use microcode the same way as it's used today. The decoding isn't as strictly separated from execution logic. Example 1: 6502 The 6502, for example, has a 'rather' simple structure built from a timing circuit counting instruction cycle and ...


19

The 5100 had programmable microcode which could be used to implement crypto-specific opcodes1,2,3. Then there's the whole John Titor4,5 thing... 1 Such as population count 2 I'm unaware of anyone actually having done so. 3 Certain agencies are very interested in such things though. 4 Perhaps it wasn't code-breaking in the traditional sense. If you have ...


18

[...] had these opr instructions, which contained many bitfields which encoded something like "subinstructions"[...] What you describe is basically a (V)LIW instruction format - at least that's what it might be called today. That's what computers started out with. Separate bits for each function to be applied to the value addressed. The DEC is somewhat of ...


17

The PDP-7 was a one address machine. All instructions occupied 18 bits. The operations that manipulated the accumulator didn't reference memory, and therefore didn't need an address. But the address bits were in the instruction anyway, because all instructions were encoded in an 18 bit word. So why not use these unused bits to get more use out of the ...


16

Quick shot, without looking it up in Visual 6502 (which would be the authorative option): Sign extend the branch offset (replicate MSB of offset), that will tell you the ALU input for the PC high byte. Possible values are 0 and -1 (all 1s), these are available as constants. Carry and sign of the branch offset together determine if an extra cycle is ...


15

There are retro computers that have readable and writeable microcode, but not the ones you mentioned in your question. And the ability to change the microcode was extremely rare in the kinds of CPUs you are thinking about. I'll describe the way the microcode worked in the 6502, or the Decode ROM as it's usually called there (same concept, different name). ...


10

I was in college when the 8086 and 6502 came out, and took a digital electronics course at that time in which I designed a simple CPU using microprogramming techniques. From studying the 8086 and 6502, I could imagine that they were microcoded, but there was no way to tell for sure from the outside. Microcode, if it existed, was all burned into the chip ...


10

In general most instructions on the 6500 series take as many cycles as there are memory accesses, with a lower limit of two. This means no instruction will execute in less than two cycles (*1). The mentioned ADC gives a nice example, as it offers almost all addressing modes: Mode Example Length | Cycles ...


9

Assuming you’re asking: what can the 6502 be seen to be doing by an external observer, then the data sheet has a full breakdown of bus activity per cycle per addressing mode; that was long ago transcribed into ASCII form by the Commodore community and is now often sourced from that 64doc.txt. Do a search in that document for “Instructions accessing the stack”...


8

The canonical examples for early microcoded CISC microprocessors are probably the Intel 8086 and the Motorola 68000. Of the two, the 8086 is the simpler (29K transistors vs. 70K in the 68000). But both of these CISC processors will present challenges in terms of their complexity and in terms of finding resources about the proprietary internal microcodes. ...


8

But it's not a ROM; [...] it's actually a PLA Then again, a ROM and a PLA is essentially the same technology. What differs here is not only the decoding, but that in case of the 6502 only the decoding part is present and it's not monotone. Such compression is obviously useful. Die space is expensive True. But it's worth to note that the cited answer says &...


6

I was VAX Architect for six years in the late '80s, and at least during my tenure, Raytheon was the only company licensed to design VAX-compatible processors, for producing MIL-SPEC machines. They did design at least one (a high-performance processor with a very interesting microarchitecture that translated VAX instructions on the fly into a RISC-like ...


6

Two interconnected moments in history with the popularity of microcode in microprocessors need to be distinguished: Firstly, the ratio of price, volume and speed of various types of memory; Secondly, the ratio of manual labor and the development of automation, including the theory of compilers. The heyday of the microcode came at a time when the means for ...


6

One example is the 6502. It fetches an opcode, and then while storing the opcode in internal memory, fetches some argument which may be 1 or 2 bytes. This is not hard to achieve, it is not a Herculean task. While the instruction executes, the operand might be stored in another register, routed through the ALU or other circuitry, or whatever. Another ...


6

I think the original argument (both in the John Titor hoax and in Steins;Gate) goes like this: The IBM 5100 can emulate the IBM mainframe ISA (that's true, and that's how the APL running on the IBM 5100 was implemented: They took the mainframe APL implementation, because they didn't have enough time to develop a native APL. That also makes it slow...), and ...


5

There is at least one documented example of one hardware design being used as two different processors via customer specific microcode: Some very small, late implementations of IBMs S/370 (eg those sold as PC expansion cards) used an 68000 with a different microcode as the main CPU.


5

With the help of the PDF I found in @dirkt's link, I'm able to answer my question. Yes, there are internal T signal states, each of them running in the active phase of two non overlapping 8 MHz internal clocks. But no, you can't process data at the rate I anticipated. I forgot about bus precharge (extract from the PDF): I expect that it's the same for every ...


4

For those interested in the hands-on use of microcode, including how to implement a CPU (1802 - which was NOT microcoded, but a FSM control unit) and a display controller, I developed a compiler that generates the [horizontal] microcode and instruction mapper memory. https://hackaday.io/project/172073-microcoding-for-fpgas


3

Note: Strictly speaking, my answer below doesn't answer the question asked, because what the OP was referring to was the instructions reserved for customer use, rather than those it reserved for DEC, which is what my reply was about. The corrected version of my answer, for the "XFC" opcodes (with a prefix of hex 0xFC) would be not as far as I ...


3

As I understand it, later chips like the 8086 and 68000 use microcode of the conventional ROM variety. This is simply not true. 68000 CPU used a combination of PLA-driven decoding and ROM-driven microcode engine. Look https://dl.acm.org/doi/10.1145/1014198.804299 for reference (remember that there is Sci-Hub at your service if you know DOI: https://sci-hub....


3

AFAIR it's Carry XOR Sign (of the offset). If this yields true, it's increment when Carry, otherwise decrement.


3

Another good example of this basic architecture is the HP2100 series, which had a series of bit-field instructions that performed things like test-and-branch. They could combine up to eight instructions in some cases. This basic idea was relatively common in the few minicomputers I've looked at. The reason they fell out of favor was that they require ...


3

[Preface: This question is independent of word size or CPU, and in no way RC.SE specific, but a basic lesson about processor design, so it might be more appropriate to ask in SO, CS or EE] It's as simple as 1, 2, 3. A two word immediate operation could run like this: Fetch one word from [PC] into OPCODE register and increment PC OPCODE-Register can now ...


2

"You have to fetch another byte while storing the first, which seems frankly impossible to me." In simple words CPU is storing first byte (opcode) in internal register(s). Most (or maybe all) CPUs are realized as finite-state machine (https://en.wikipedia.org/wiki/Finite-state_machine). Most known CPU states are FEtch, Instruction Decode, EXecute, MEMory ...


2

The length of the ADC Immediate is 2. One for the opcode $69 and one for the immediate. At the very least, this requires two bus cycles to fetch. On a "simple" processor, an instruction can't take fewer cycles than the number of bus cycles that need to be performed to do the work of that instruction.


1

It is quite typical in chip designs using common IC technology nodes of that era (around 5000 NM NMOS) to require a separate clock phase to precharge any bus signals before they can be used for logic signaling. The NMOS pull-ups (if any!) to a logic high level were mostly too weak or too slow to accomplish this in a single clock cycle without the extra ...


1

Modern CPU architectures also need to facilitate things like memory protection, so they need to implement restrictions on what machine code can and cannot effect depending on context. You do not want normal application code to be able to mess with other code in a multiuser/multitasking environment, and you certainly do not want it to be able to crash the ...


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