Not all of the original co-processors were for floating point math. Intel itself offered an I/O coprocessor for the 8088 and 8086 called the 8089. Part of the reason it didn't do as well as the 8087 is that the PC included an empty socket for an 8087, but no support for the 8089.
If you broaden the conversation out beyond just the 8086 generation of chips, ...
The Alpha team set out to create a high-performance architecture, planned to last for 25 years and allow for 1000-performance increase over those 25 years. So they placed some long bets, starting with the 64-bit design (which cost performance but ensured long-term viability). It wasn’t designed to compete with x86 (which wasn’t perceived as a viable long-...
TL;DR: It's the pipeline.
The 80486 contains parallel operating stages for decoding, operand fetch, execution and write back. So while an ADD reg,reg does take 3 clocks to perform, as it did in the original 8086, its execution overlaps with the previous/next operation, so the CPU can crank out one ADD reg,reg per clock.
The Long Read
(Caveat, there's a whole ...
The DEC PDP-8 family was 12-bit, and so was the Intersil 6100, a single-chip CMOS implementation of the PDP-8 ISA.
There have been many 24-bit DSP-type processors, from Motorola, Microchip, Analog Devices, among others.
The Burroughs large systems (mainframes), starting with the B-5000 in 1961, used an ISA called "E-mode", which had 48-bit data ...
Stephen Kitt has done what seems to me an excellent job of outlining features and when they were introduced. I'll take a slightly different tack, instead picking a single point in time, and pointing out differences between the two at that time.
I'm going to choose the 21164 as the Alpha to compare. It came out in January of 1995. It had a 266 MHz clock ...
The 6502 CPU is just one piece of the puzzle
Emulators emulate entire machines, not merely CPUs. Even the likes of QEMU emulate an entire generic computer.
It helps if you think of the Apple II and NES not as singular units but as networks of components. The CPU, graphics unit, RAM and so on all have communications to each other and do so at a very fast ...
Reasoning about the usage of existing packages
Adding a few hundred transistors for multiplexing is approximately free compared to buying production machinery for several millions - way before the first chip can be made.
Creating a new chip (family) is for sure a risky bet on the future and takes some investment. Keeping this investment ...
How was microcode implemented in retro processors such as the Z80 or 8080?
None of these chips (likewise 6800 and 6502) use microcode the same way as it's used today. The decoding isn't as strictly separated from execution logic.
Example 1: 6502
The 6502, for example, has a 'rather' simple structure built from a timing circuit counting instruction cycle and ...
specifically after the 8-bit byte became the industry standard?
There's no clear point of time where the 8-bit byte became a standard, since it's still just a de facto standard nowadays¹. However probably the 1970s were the transition time due to many newer architectures and standards with 8-bit bytes, and if you look at the word size list then you'll see ...
There are many answers to this and none might satisfy you.
First of all, an emulator doesn't just do a CPU, but a machine. The same way you can't run an NES game on an Apple II. So while one emulator may do multiple machines, different emulators can do the job as well.
Furthermore, there are different target platforms. Linux isn't Windows which again isn't ...
No, they cannot.
They share both the data and the address bus of the C128, so they can only run exclusively at any one point in time.
The address bus is apparently directly connected, the data bus of the Z80 through a set of latches to the data bus of the rest of the system.
In CP/M mode, the 8502 is handling keyboard, screen and printer and serial ...
I don't know details of the Sharp PC-G830 specifically but the technique used to address more than 64K with a 16-bit address bus is called "bank switching".
This involves setting up some portions of memory to be switchable via an I/O port line and then the application program organizes things in memory such that different sections can be switched ...
The HALT condition does not (at least on retro CPUs) consume considerably less power than normal execution does.
One very obvious use case is synchronizing program flow with external (hardware) events. The main use case of the HALT instruction is thus "wait for an interrupt".
A prominent example outside embedded systems is synchronizing video ...
Alan Cox mentions in this post having seen a hard drive interface that plugged into the 8087 socket (for computers with no expansion slots).
I've checked various issues of Amstrad PC magazine. PPC hard drive upgrades are advertised by ABSI Consultants, Alfa Electronics Ltd, Dovetail DST, International Hard Discs, and Stratum Technology Limited. I have a PPC ...
Here’s the list of main technologies used:
4004: 10µm PMOS;
4040: 10µm PMOS;
8008: 10µm PMOS;
8080: 6µm NMOS (faster than PMOS, and TTL-compatible);
8085: 3.2µm NMOS, then HMOS (“H” variants);
8086: 3.2µm NMOS, then HMOS (in three iterations) and CHMOS (static variants);
80186: 3.2µm HMOS and CHMOS;
80286: 1.5µm HMOS (also CMOS, at least from other ...
I don't think there ever were any incompatible co-processors which used the same sockets and I/O mechanisms as the Intel co-processors.
There were other incompatible co-processors, at least for the 386 and 486: the Weitek 3167 and 4167 (Wikipedia also mentions the 1067 for 286s, and 1167 and 2167 for 386s, but I don't know anything about them). These ...
Full, hardware-assisted virtualisation, with the intention of supporting hypervisors running operating systems without requiring para-virtualisation, was added to micro-processors relatively recently. (Many RISC-style architectures were virtualisable following Popek and Goldberg’s criteria, and were used in high-end partitionable systems, but with external ...
First, it is not true that the 486 executes instructions in a single cycle. The 80486 is a pipelined architecture, so it's more accurate to say that most instructions can start one cycle after the preceding instruction has started. The pipeline length of an 80486 is 5 stages (IF → ID1 → ID2 → EX → WB). This means that an instruction ...
Any CPU that is fully-static can be clocked down to 0 Hz and still function. Such CPUs are in wide use today. Here are some examples:
Used in a few early micros, as an embedded processor, and in space applications such as Galileo (Jupiter) and Magellan (Venus). It also was the initial platform for CHIP-8.
A variant of the 386 ...
What was the halt instruction in early CPUs such as the Z80 and 8080 used for?
Stopping the system in a known state to allow a clean restart/react to external sources.
It's a very useful feature for embedded systems that react to external sources, but also as idle state for a more conventional kind of multitasking environment.
What use is it to enter a ...
In the 1988 Report on the 65c832, Mensch described the 65c832 as a back-burner project with an uncertain timeline:
Since WDC is not a gigantic conglomerate, it has limited
resources. If all your manpower, time, and money are going towards the
development of the 65c265, you don't have any left for the '832. That's
exactly what was happening ...
Going with the spirit of the question.
A quick glance at Wikipedia's Microprocessor Chronology we find:
PPS-4 from Rockwell at 200 kHz
PPS-8 from Rockwell at 256 kHz
TMS 1000 from TI at 400 kHz
PPS-25 from Fairchild at 400 kHz
IMP-4 from National at 500 kHz
8008 from Intel at 500 kHz
IMP-8 & -16 from National at 715 kHz
the 4004 and 4040 from Intel at ...
In addition to the i8087 & i8089, intel had the i80130 and i80150 "Operating System Coprocessors". These were single-chip bundled timers and irq controllers that had a subset of the iRMX-86 ('130) or CP/M-86 ('150) in ROM.
Quick shot, without looking it up in Visual 6502 (which would be the authorative option):
Sign extend the branch offset (replicate MSB of offset), that will tell you the ALU input for the PC high byte. Possible values are 0 and -1 (all 1s), these are available as constants.
Carry and sign of the branch offset together determine if an extra cycle is ...
Your question assumes that CPUs with more than 40 pins were a rarity in the 1970s, but this was common for early 16-bit CPUs. Both the TI TMS9900 and the Motorola 68000 had 16-bit external data busses, no multiplexing, and came in a 64-pin DIP package.
The thing that was common at this time was DIP packaging. And the number of pins on a DIP package was ...
Coincidentally, I found this explanation reading through Microprocessor Interfacing Techniques 3rd Ed 1979 by Zaks and Lesea page 16:
The Standard Microprocessor System
Throughout this book, reference will be made to a “standard microprocessor.” The “standard” microprocessor today is the 8-bit microprocessor. Examples are the Intel 8080, 8085, the ...
The Garrett AiResearch MP944 has a good claim to be the first microprocessor. It's 20-bit, designed from 1968 to 1970, and classified until 1998, so it is not well known.
The Toshiba TLCS-12 family was designed from 1971-73 and is 12-bit. The Intersil 6100 has already been mentioned, it was a single-chip implementation of the older 12-bit DEC PDP-8.
There are retro computers that have readable and writeable microcode, but not the ones you mentioned in your question. And the ability to change the microcode was extremely rare in the kinds of CPUs you are thinking about.
I'll describe the way the microcode worked in the 6502, or the Decode ROM as it's usually called there (same concept, different name). ...
As mentioned, being able to operate static isn't tied to production process, but the logic design. Thus there were of course static CPUs. A good example might be the Valvo-Signetics 2650 one of the more successful of the lesser known ones. Another example might be Texas' 9900, but I'm not entirely sure without checking its data sheet.
There are a number of approaches that can allow a CPU with a 16-bit address bus to address more than 64kBytes of memory:
Bank Switching - explained in another answer,basicaly switching for example 8- or 16-kBytes blocks back and forth into the addressable range, so in effect exchanging the blocks with ones that are currently paged in. Some computers could ...