72

TL;DR: It's the pipeline. The 80486 contains parallel operating stages for decoding, operand fetch, execution and write back. So while an ADD reg,reg does take 3 clocks to perform, as it did in the original 8086, its execution overlaps with the previous/next operation, so the CPU can crank out one ADD reg,reg per clock. The Long Read (Caveat, there's a whole ...


25

Here’s the list of main technologies used: 4004: 10µm PMOS; 4040: 10µm PMOS; 8008: 10µm PMOS; 8080: 6µm NMOS (faster than PMOS, and TTL-compatible); 8085: 3.2µm NMOS, then HMOS (“H” variants); 8086: 3.2µm NMOS, then HMOS (in three iterations) and CHMOS (static variants); 80186: 3.2µm HMOS and CHMOS; 80286: 1.5µm HMOS (also CMOS, at least from other ...


18

In the 1988 Report on the 65c832, Mensch described the 65c832 as a back-burner project with an uncertain timeline: Since WDC is not a gigantic conglomerate, it has limited resources. If all your manpower, time, and money are going towards the development of the 65c265, you don't have any left for the '832. That's exactly what was happening ...


18

First, it is not true that the 486 executes instructions in a single cycle. The 80486 is a pipelined architecture, so it's more accurate to say that most instructions can start one cycle after the preceding instruction has started. The pipeline length of an 80486 is 5 stages (IF → ID1 → ID2 → EX → WB). This means that an instruction ...


11

On the 8088 and 8086, execution involves two parallel processes--memory access and internal computation--and will be limited by the speed of whichever is slower. Generally, on the 8088 execution speed will be limited by memory access, while the 8086 will be better balanced. Every memory cycle on the 8088 or 8086 takes a minimum of four cycles, and on most ...


11

I suspect this isn’t quite the answer you’re looking for, but there’s no need to wait for RISC... What was the first microprocessor that could do ALU operations (independent of the value being loaded, e.g. in other registers) while a load from memory was in progress? I think the answer is the 6502, which fetches the next instruction before the current ...


10

In general most instructions on the 6500 series take as many cycles as there are memory accesses, with a lower limit of two. This means no instruction will execute in less than two cycles (*1). The mentioned ADC gives a nice example, as it offers almost all addressing modes: Mode Example Length | Cycles ...


9

Assuming you’re asking: what can the 6502 be seen to be doing by an external observer, then the data sheet has a full breakdown of bus activity per cycle per addressing mode; that was long ago transcribed into ASCII form by the Commodore community and is now often sourced from that 64doc.txt. Do a search in that document for “Instructions accessing the stack”...


9

I am afraid that the answer is "it could take any time, depending on circumstances and the real WAIT condition". WAIT states have unpredictable length, so there is no exact way to answer your question. The general answer, theoreticaly valid for every CPU (and really valid for the most of 8bit CPUs), is: Take an "instruction timing chart" ...


8

I suppose you have heard of the draft datasheet of the 65832? https://downloads.reactivemicro.com/Electronics/CPU/W65C832%20CPU%20Datasheet%20v2.0.pdf Apple was the main customer of the 65816 (for Apple //gs) which needed to be compatible with 6502. They had no need of a 32bits version as Macintosh had already chosen the MC68000 family which is a sounder ...


8

But it's not a ROM; [...] it's actually a PLA Then again, a ROM and a PLA is essentially the same technology. What differs here is not only the decoding, but that in case of the 6502 only the decoding part is present and it's not monotone. Such compression is obviously useful. Die space is expensive True. But it's worth to note that the cited answer says &...


7

I have the following assembly code for 8086 To start with basic timing for 8086 (*1) in CPU clocks is 21 clock cycles. MOV AL,[BX] (*2) 13 cycles, consisting of 8 cycles for the instruction (MOV reg8,mem) plus 5 to calculate the address from [BX]. Since it's a byte access, no penalty for misalignment can happen. OUT DX, AL 8 cycles, all for the ...


6

Intel 8008 CPU has an internal stack, implemented as an 8 x 16-bit scratchpad. No, it's entries are 'only' 14 bit long, as all addressing on the 8008 supports only 14 bit (*1). How does it work exactly? Is there any "invisible 3-bit stack pointer"? Yes. In reality it's not a stack pointer, but selects the active PC. A three-bit address pointer ...


6

Two interconnected moments in history with the popularity of microcode in microprocessors need to be distinguished: Firstly, the ratio of price, volume and speed of various types of memory; Secondly, the ratio of manual labor and the development of automation, including the theory of compilers. The heyday of the microcode came at a time when the means for ...


6

The repeated-addition algorithm you describe is not the usual way. Instead, think of long multiplication, but in base 2 instead of base 10. The shift instructions available in most CPUs are useful here. Here's how you might do it on a 6502: Mul8x8to16: LDX #8 LDA #0 STA resultHi @loop: ; shift result up by one place ASL A ROL resultHi ; ...


6

The Motorola 68882, while not strictly a microprocessor but a coprocessor, was explicitly designed to handle loads and format conversions in parallel with arithmetic operations. This was, in fact, the main advantage it held over its immediate predecessor, the 68881. The 68882 was available by at least 1988, as the Macintosh IIx included it. If you ...


4

I want to know what are the possible ways of putting CS,SS,DS and ES in RAM Each of them can point to any location in RAM dividable by 16 (ending in xxxx0). Since each of them is 16 bits, there are 65536 locations to point them to, resulting in a total of 2^64 possible combinations, right? Are there any specific ways that we could not put CS,SS,DS and ES ...


4

It seems that some of the information you have doesn't apply to the SAP-2. Earlier in the book, it said that to execute a decrement instruction, you must load the value you want to decrement in A, subtract 1, and then load it back into the designated register. The Simple As Possible SAP-2 computer has dedicated decrement instructions. Section 11-4 "...


4

For those interested in the hands-on use of microcode, including how to implement a CPU (1802 - which was NOT microcoded, but a FSM control unit) and a display controller, I developed a compiler that generates the [horizontal] microcode and instruction mapper memory. https://hackaday.io/project/172073-microcoding-for-fpgas


4

At some point before 1990 the idea seems to have first surfaced as a 'report' about 6502 chronology and future processors might suggest. It includes not only information about the ghostly 6516, but also information about a 65832 which should have more features than the datasheet showed. There was also no substantial follow up. The project might have gotten ...


3

Datasheet for the Intel 8008 CPU mentions that the Carry (C) flag is affected with the logic operations (AND, OR, XOR), but it does not make any sense. I believe Carry will be zeroed, but I have no proof of this conclusion. First, the manual does not say anything special about logic operations but states: The result of the ALU instructions affect all of the ...


3

As I understand it, later chips like the 8086 and 68000 use microcode of the conventional ROM variety. This is simply not true. 68000 CPU used a combination of PLA-driven decoding and ROM-driven microcode engine. Look https://dl.acm.org/doi/10.1145/1014198.804299 for reference (remember that there is Sci-Hub at your service if you know DOI: https://sci-hub....


2

The length of the ADC Immediate is 2. One for the opcode $69 and one for the immediate. At the very least, this requires two bus cycles to fetch. On a "simple" processor, an instruction can't take fewer cycles than the number of bus cycles that need to be performed to do the work of that instruction.


2

My personal experience with the Alpha AXP was when I attended a presentation in the Detroit area during the introduction of the product many years ago. It was a video presentation and it showed the president of DEC on a stage demonstrating the capabilities of the system. He had a projection display screen that was attached to the computer, and the computer ...


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