75

The Alpha team set out to create a high-performance architecture, planned to last for 25 years and allow for 1000-performance increase over those 25 years. So they placed some long bets, starting with the 64-bit design (which cost performance but ensured long-term viability). It wasn’t designed to compete with x86 (which wasn’t perceived as a viable long-...


72

TL;DR: It's the pipeline. The 80486 contains parallel operating stages for decoding, operand fetch, execution and write back. So while an ADD reg,reg does take 3 clocks to perform, as it did in the original 8086, its execution overlaps with the previous/next operation, so the CPU can crank out one ADD reg,reg per clock. The Long Read (Caveat, there's a whole ...


51

Stephen Kitt has done what seems to me an excellent job of outlining features and when they were introduced. I'll take a slightly different tack, instead picking a single point in time, and pointing out differences between the two at that time. I'm going to choose the 21164 as the Alpha to compare. It came out in January of 1995. It had a 266 MHz clock ...


24

Here’s the list of main technologies used: 4004: 10µm PMOS; 4040: 10µm PMOS; 8008: 10µm PMOS; 8080: 6µm NMOS (faster than PMOS, and TTL-compatible); 8085: 3.2µm NMOS, then HMOS (“H” variants); 8086: 3.2µm NMOS, then HMOS (in three iterations) and CHMOS (static variants); 80186: 3.2µm HMOS and CHMOS; 80286: 1.5µm HMOS (also CMOS, at least from other ...


18

First, it is not true that the 486 executes instructions in a single cycle. The 80486 is a pipelined architecture, so it's more accurate to say that most instructions can start one cycle after the preceding instruction has started. The pipeline length of an 80486 is 5 stages (IF → ID1 → ID2 → EX → WB). This means that an instruction ...


17

In the 1988 Report on the 65c832, Mensch described the 65c832 as a back-burner project with an uncertain timeline: Since WDC is not a gigantic conglomerate, it has limited resources. If all your manpower, time, and money are going towards the development of the 65c265, you don't have any left for the '832. That's exactly what was happening ...


11

Alpha fizzled in the face of the HP/Intel partnership pushing their Itanium 64-bit architecture I think it's important to note that during this period, there was a widespread belief that the VLIW approach was "the next RISC". Existing RISC approaches were growing into the millions of transistors and the outright performance gap that existed in the 1990s ...


11

On the 8088 and 8086, execution involves two parallel processes--memory access and internal computation--and will be limited by the speed of whichever is slower. Generally, on the 8088 execution speed will be limited by memory access, while the 8086 will be better balanced. Every memory cycle on the 8088 or 8086 takes a minimum of four cycles, and on most ...


9

I am afraid that the answer is "it could take any time, depending on circumstances and the real WAIT condition". WAIT states have unpredictable length, so there is no exact way to answer your question. The general answer, theoreticaly valid for every CPU (and really valid for the most of 8bit CPUs), is: Take an "instruction timing chart" ...


8

I suppose you have heard of the draft datasheet of the 65832? https://downloads.reactivemicro.com/Electronics/CPU/W65C832%20CPU%20Datasheet%20v2.0.pdf Apple was the main customer of the 65816 (for Apple //gs) which needed to be compatible with 6502. They had no need of a 32bits version as Macintosh had already chosen the MC68000 family which is a sounder ...


7

I have the following assembly code for 8086 To start with basic timing for 8086 (*1) in CPU clocks is 21 clock cycles. MOV AL,[BX] (*2) 13 cycles, consisting of 8 cycles for the instruction (MOV reg8,mem) plus 5 to calculate the address from [BX]. Since it's a byte access, no penalty for misalignment can happen. OUT DX, AL 8 cycles, all for the ...


7

But it's not a ROM; [...] it's actually a PLA Then again, a ROM and a PLA is essentially the same technology. What differs here is not only the decoding, but that in case of the 6502 only the decoding part is present and it's not monotone. Such compression is obviously useful. Die space is expensive True. But it's worth to note that the cited answer says &...


6

Intel 8008 CPU has an internal stack, implemented as an 8 x 16-bit scratchpad. No, it's entries are 'only' 14 bit long, as all addressing on the 8008 supports only 14 bit (*1). How does it work exactly? Is there any "invisible 3-bit stack pointer"? Yes. In reality it's not a stack pointer, but selects the active PC. A three-bit address pointer ...


6

I was at HP when the Alpha cancellation decision was made. In fact I was part of a team that ran comparative HPC benchmarks on Alpha and x86. The fact was that by 1999 the x86 Pentium-II was matching the Alpha in floating point performance. This was reported by objective groups, e.g. Dongarra et al. Unfortunately the Alpha ecosystem was 10x more ...


6

Sure this is about Motorola? Could it be have been about a similar sounding manufacturer, like Mostek? Because the first to come to mind would be Zilogs Z80, which was first manufactured by Mostek, as Zilog had no production line of its own. The description about being dedicated to fast interrupt handling is also exactly what the Z80 implementation was ...


6

The repeated-addition algorithm you describe is not the usual way. Instead, think of long multiplication, but in base 2 instead of base 10. The shift instructions available in most CPUs are useful here. Here's how you might do it on a 6502: Mul8x8to16: LDX #8 LDA #0 STA resultHi @loop: ; shift result up by one place ASL A ROL resultHi ; ...


5

Z80 and 6502 are complete different CPUs in terms of clock and cycle structure. There is no sense in comparing them at this level. To solve your problem you need to focus only on your Z80 system, its instructions and their timing in relation to the video frame you want to create/manipulate. With 4 MHz each clock cycle is 250 ns. Using this on 50 Hz 625 ...


5

Two interconnected moments in history with the popularity of microcode in microprocessors need to be distinguished: Firstly, the ratio of price, volume and speed of various types of memory; Secondly, the ratio of manual labor and the development of automation, including the theory of compilers. The heyday of the microcode came at a time when the means for ...


4

At some point before 1990 the idea seems to have first surfaced as a 'report' about 6502 chronology and future processors might suggest. It includes not only information about the ghostly 6516, but also information about a 65832 which should have more features than the datasheet showed. There was also no substantial follow up. The project might have gotten ...


4

It seems that some of the information you have doesn't apply to the SAP-2. Earlier in the book, it said that to execute a decrement instruction, you must load the value you want to decrement in A, subtract 1, and then load it back into the designated register. The Simple As Possible SAP-2 computer has dedicated decrement instructions. Section 11-4 "...


4

For those interested in the hands-on use of microcode, including how to implement a CPU (1802 - which was NOT microcoded, but a FSM control unit) and a display controller, I developed a compiler that generates the [horizontal] microcode and instruction mapper memory. https://hackaday.io/project/172073-microcoding-for-fpgas


3

Datasheet for the Intel 8008 CPU mentions that the Carry (C) flag is affected with the logic operations (AND, OR, XOR), but it does not make any sense. I believe Carry will be zeroed, but I have no proof of this conclusion. First, the manual does not say anything special about logic operations but states: The result of the ALU instructions affect all of the ...


3

As I understand it, later chips like the 8086 and 68000 use microcode of the conventional ROM variety. This is simply not true. 68000 CPU used a combination of PLA-driven decoding and ROM-driven microcode engine. Look https://dl.acm.org/doi/10.1145/1014198.804299 for reference (remember that there is Sci-Hub at your service if you know DOI: https://sci-hub....


3

Ten billion can be represented in 34 bits, never mind 64. The hexadecimal representation (in which each digit contains four bits) is 0x2540BE400. The maximum (unsigned) 64-bit integer is 18446744073709551615. This is (2^64)-1, which is essentially the square of (2^32)-1, which is "about" 4 billion. In general, you can estimate that every 10 bits ...


2

There is the 6809 which has 2 Stack Pointers, SP and USP (user stack pointer). I think the 68K can manipulate the pointers such that the Stack address can be exchanged with it's other registers.


2

My personal experience with the Alpha AXP was when I attended a presentation in the Detroit area during the introduction of the product many years ago. It was a video presentation and it showed the president of DEC on a stage demonstrating the capabilities of the system. He had a projection display screen that was attached to the computer, and the computer ...


2

One little known fact is that what become PostgreSQL was done on Alpha workstations with 64MB of RAM. I forget the model number of the workstations but they were small desktop machines. I was the system manager for the Postgres Research Group at UC Berkeley. We also had a couple of Alpha servers. The Alpha hardware (and software) worked quite well. We were ...


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