The DEC PDP-8 family was 12-bit, and so was the Intersil 6100, a single-chip CMOS implementation of the PDP-8 ISA.
There have been many 24-bit DSP-type processors, from Motorola, Microchip, Analog Devices, among others.
The Burroughs large systems (mainframes), starting with the B-5000 in 1961, used an ISA called "E-mode", which had 48-bit data ...
specifically after the 8-bit byte became the industry standard?
There's no clear point of time where the 8-bit byte became a standard, since it's still just a de facto standard nowadays1. However probably the 1970s were the transition time due to many newer architectures and standards with 8-bit bytes, and if you look at the word size list then you'll see ...
Full, hardware-assisted virtualisation, with the intention of supporting hypervisors running operating systems without requiring para-virtualisation, was added to micro-processors relatively recently. (Many RISC-style architectures were virtualisable following Popek and Goldberg’s criteria, and were used in high-end partitionable systems, but with external ...
Were there ever 12-, 24-, 48-, etc bit processors?
Yes! See https://en.wikipedia.org/wiki/Word_(computer_architecture) for an enumeration of historical word sizes.
Before the 8-bit byte became standard, computers were not byte addressable, only word addressable.
Originally, computation was mostly numeric oriented, so a (sometimes double) word data size ...
The Garrett AiResearch MP944 has a good claim to be the first microprocessor. It's 20-bit, designed from 1968 to 1970, and classified until 1998, so it is not well known.
The Toshiba TLCS-12 family was designed from 1971-73 and is 12-bit. The Intersil 6100 has already been mentioned, it was a single-chip implementation of the older 12-bit DEC PDP-8.
Almost impossible to tell. Both CPUs have been sold by quite a lot of manufacturers in many variations - including knockoffs modified in some way to avoid royalties.
One hint might be the claim of 5 to 10 billion (*1) on the WDC site:
Since WDC is nowadays the major licensor (*2) and still can only give it with such a huge uncertainty, I doubt anyone will ...
The Popek and Goldberg virtualisation requirements are usually dug out for discussions of this kind, but it is more of a quick rule-of-thumb and it turns out that doing virtualisation well requires a more than their rules, and with ingenuity one can get away with less. Ultimately, there is no single answer because it's a case of evolution with it being ...
Andrew Tanenbaum wrote two papers about operand encoding, instruction sizes, and the representations of structured programming constructs, which sounds like what you’re looking for: Implications of structured programming for machine architecture (Communications of the ACM, March 1978) and Efficient encoding of machine instructions (ACM SIGARCH Computer ...
KDF9 was 48 bits, though this probably predates the 8-bit byte standard.
KDF9 did not have 'a' character code; codes were device-specific. Printer code was for example 6 bits. However, the PROMPT file system (and ELDON2 which adopted the same) used 8 bit 'characters', with the benefit that Algol basic symbols such as underlined procedure were stored as ...
Yes, there were other co-processors for the IBM PC computer other then Intel 8087 NPU/FPU Units. Many of them had additional circuity with some RAM and a ROM chips. The ROM chips on some of them contained an FPU emulation program if it was using a standard microprocessor other than a Intel model. Others had a BIOS extension for the system.
Some older issues ...
Microchip's PIC family has processors with lots of weird word sizes. For instance for the PIC16F1454/5/9:
program counter is 15 bits (and stack is thus 15-bits wide as well)
instruction words are 14 bits
data addresses are 12 bits (7 bits for bank and 5 bits within the bank)
but data words are 8 bits
The main problem I found with having only one index register on the 6800 was having to constantly load and save source and destination addresses when doing a memory copy (though you could use SP as extra 'index' register so long as interrupts were disabled). Another thing that didn't help was that many instructions took longer than they could have.
Yes it is possible to have an IDE controller on a 8087 NPU (FPU) coprocessor socket.
Most of these adapters had a circuit to switch in a BIOS and RAM cache Overlay when the IDE controller logic required it.
Another example of this would be any expansion card that used the Dec. Rainbow 100 computers memory expansion card slot for peripherals. The card ...
I can give you an overview of the external control signals that appear on the pins of the 6502, but you'll need to go to somewhere like visual6502.org to get an idea of the internal signals.
There are three control signals dedicated to the clock
The first is an input, the system clock. ø1 is an output: ø0 inverted but with the high pulse slightly ...
I'd just go with the datasheet (Rockwell version, Commodore Version) as it contains everything needed. But there is THE book to read:
The MOS MCS6500 Family Hardware Manual
One hint, in all respect and seriousness, if you have a hard time to give the signals a basic meaning (as noted in your comment), then simulating a CPU might be above your level.
Regarding the 8051:
One in most OSD-capable CRT monitors or television sets ever sold.
One in most pre-DVD CDROM drives ever sold.
One in most pre-2000s hard drives.
A predecessor of the 8051 (the 8042. An 8048 derivative. The 8048 is NOT an 8051 per se, the 8051 was developed as a solution to do what the 8048/-42 could not do well and is NOT an extended ...
The W65C02 data sheet does explain it (p. 9):
3.4 Interrupt Request (IRQB)
The Interrupt Request (IRQB) input signal is used to request that an interrupt sequence be initiated. The program
counter (PC) and Processor Status Register (P) are pushed onto the stack and the IRQB disable (I) flag is set to a "1"
disabling further interrupts before ...
Ten billion can be represented in 34 bits, never mind 64. The hexadecimal representation (in which each digit contains four bits) is 0x2540BE400.
The maximum (unsigned) 64-bit integer is 18446744073709551615. This is (2^64)-1, which is essentially the square of (2^32)-1, which is "about" 4 billion.
In general, you can estimate that every 10 bits ...
The ICL 1900 series was indeed 24-bit words, used as four 6-bit characters. Using 8-bit media like papertape required escape characters called alpha, beta and delta to switch case and special characters.
ICL replaced 1900s with 2903 and ME29, which was a 32-bit architecture machine cut back to 24 bits for compatibility with 1900s.
ICL also had office ...
The CPU also has a special "high page" load instruction that works like the 6800/6502 zero page or 6809 direct page addressing modes.
Looks like that's where the Nintendo guys came from, doesn't it? It couldn't be at zero, as thats where the vectors are stored (basically the reverse layout of a 6502, isn't it?)
This makes it one byte shorter (and thus ...
What does full virtualization mean in this context?
I guess a more general approach may be helpful.
First off, as soon as virtualization leaves the topic of the (core) CPU, anything becomes machine and implementation specific - so it's not only relying on the CPU itself. Further, even such a virtualization does usually need an hypervisor, another OS, ...
The Game Boy is an SoC; with the exception of the on-board work RAM
and video RAM (8 KB each), the CPU and all on-board peripherals are
contained on a single chip. (The cartridge adds external ROM and
optionally a memory bank controller, RAM and other peripherals.)
Thus, the HRAM is on the CPU die. Is not inherently faster than
external memory: all accesses ...
Another important thing is cycle accuracy. Not every emulator is cycle-exact!
While it might seem unimportant, without it some games are impossible to play
Let's take the case of Speedy Gonzales. This is an SNES platformer with no save functionality, and it's roughly 2-3 hours long. At first glance, it appears to run fine in any emulator. Yet once you ...