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The Game Boy is an SoC; with the exception of the on-board work RAM and video RAM (8 KB each), the CPU and all on-board peripherals are contained on a single chip. (The cartridge adds external ROM and optionally a memory bank controller, RAM and other peripherals.) Thus, the HRAM is on the CPU die. Is not inherently faster than external memory: all accesses ...


The main problem I found with having only one index register on the 6800 was having to constantly load and save source and destination addresses when doing a memory copy (though you could use SP as extra 'index' register so long as interrupts were disabled). Another thing that didn't help was that many instructions took longer than they could have. The ...


68HC11 should be opcode compatible and it has extra index register. But using the other index register requires an extra prefix byte to indicate non-default register.


An interrupt pin of a CPU will always be an Input. After all, it's whole purpose is to tell the CPU about an interrupt pending. Wouldn't work if it's an output, would it?


The W65C02 data sheet does explain it (p. 9): 3.4 Interrupt Request (IRQB) The Interrupt Request (IRQB) input signal is used to request that an interrupt sequence be initiated. The program counter (PC) and Processor Status Register (P) are pushed onto the stack and the IRQB disable (I) flag is set to a "1" disabling further interrupts before ...


The interrupt pin is an input.

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