30

It's a bit misleading to call them "undocumented opcodes". "Accidental opcodes" would be more accurate. Instead of using microcode, the 6502 family used a programmable logic array as a lookup table to break an instruction down into a series of simpler steps. At each step of executing an instruction, the CPU would form a bit pattern from the instruction ...


29

In some cases undocumented instructions may be useful as shortcuts to accomplish tasks that are "difficult" to achieve with the official instructions. Going with the Z80, it is common practice amongst developers to make use of the undocumented instructions that allow to access index registers IX and IY as pairs of 8-bit registers (so IXh, IXl, IYh, IYl). ...


26

The 6502 was designed and manufactured before Commodore bought MOS Technology, the creator of the 6502. MOS Technology didn't originally plan to build computers. They wanted to sell the 6502 to companies who wanted to build computers. Back then, anyone planning to bring an electronic device to the market wouldn't choose any chip that didn't have multiple ...


22

More “serious and modern” CPUs than the 6502, Z80 and PDP-8 have undocumented instructions too, and they don’t necessarily cause the CPU to stop. The Intel x86 line has quite a few instructions which were initially undocumented; one very famous instruction, which can not be replaced by documented instructions, is LOADALL, which has been discussed here ...


21

In many cases, undocumented opcodes were not deliberately created, but are merely the result of designers including the minimal circuitry necessary to create a specified set of opcodes. On the 6502, for example, consider how one might go about creating the instructions LDA, LDY, and LDX. Rather than handling the three instructions separately, it would make ...


19

To a certain extent you can guess the number of cycles by counting the number of memory accesses. A 2-byte instruction will take a minimum of 2 cycles because you need to read 2 bytes. If the instruction needs to read or write a data byte add another cycle. For example, a zero-page read is a 2-byte instruction, but in addition to reading the instruction ...


16

Quick shot, without looking it up in Visual 6502 (which would be the authorative option): Sign extend the branch offset (replicate MSB of offset), that will tell you the ALU input for the PC high byte. Possible values are 0 and -1 (all 1s), these are available as constants. Carry and sign of the branch offset together determine if an extra cycle is ...


15

The 6502 has been used in huge volumes in markets that commodore never cared about competing in much - terminals for large-scale professional computing, printers and plotters (which they mostly bought in from OEMs if sold with their own computers), embedded solutions, test and industrial and scientific equipment, arcade machines ... - just as other 8 bit ...


14

I presume that these locations [Zero Page and Stack] are hard-coded into the workings of the 6502 Yup, they are. So how did this work? Simply by partial address decode. Address bit A8 was not decoded when RAM was accessed and A7 was used as chip select. This mirrored the 128 ($80) bytes two times over ZP and Stack (at $0080 and $0180) (*1). So all 128 ...


13

Yes, your assumption is correct. Like in any microcontroller design I know of, I/O lines with programmable direction are set to input on reset. The 6510 is no exception, its data direction register at address 0 is set to 0 on reset, all 6 I/O lines become inputs. The circuitry outside the processor includes a pullup resistor on the I/O lines controlling ...


10

(Caveat, this is from far away memory) In general your second assumption is right. But step by step: I can imagine one way to do it would be to have all the relevant flags serve as inputs to the decode ROM. Then BEQ and friends could be microprogrammed to work differently depending on which bits were set. Now, as the 6502 logic is more a highly (in ...


6

Not sure that this really counts as using undocumented op-codes, but might be sufficiently related to be of interest... On the 8086, there are often two ways of encoding the same instruction (especially for register-register operations). At least one shareware package (the A86/A386 assembler written by Eric Isaacson) uses this facility to "watermark" the ...


6

The only issue that comes to mind was the original Motorola vs. MOS case about the 6501 being pin compatible to the 6800. Since MOS was by then part of Commodore, their settlement not to make a compatible CPU might be referenced here, as this was of course future binding. But as the wording already suggests, the decision might be more based on a bias than ...


4

Are old 65C816s TTL compatible? If their Vih is 2.0v, they are certainly TTL-compatible. Was there some kind of change? All WDC chips seem to be verilog-reimplemented, so when they synthesized them into netlist, they've intentionally dropped TTL-compatibility of IO-pins. The reason for that might be the need to have chips working in 1.8V..5.0V range (...


3

yes ddr register is set to input on reset and because of the pullup lines for charen loram and hiram its a logical 1. take a look at the Pitfall 2 cartdrige. it works with vice 3.1 but not in 3.2. The init value of the data port register was changed from 0x3f to zero between both versions. whats happening in 3.2: the game changes ddr to output but not the ...


3

AFAIR it's Carry XOR Sign (of the offset). If this yields true, it's increment when Carry, otherwise decrement.


3

Quick answer (I can update with a cycle-by-cycle description of what happens if you need it): You can see exactly what happens in the 6502 using the in-browser simulation provided by visual6502.org in advanced mode. Enter a branch, and watch what the control lines do. You can even see where every signal is located on the chip. The 6502 has a two-stage "...


3

Commodore thought they would have such high volumes that they needed a second source because MOS Technology might not be able to reliably fab enough. Semiconductor process technology was not as reliable in those days, and manufacturing yields from any particular fab line could vary drastically, cutting chip supplies. So Commodore licensed the 6502 ...


3

You are correct that instructions of the same form follow the same pattern. Alas, I forget my original documentation sources now (perhaps this?), but these days I tend to use my emulator code as a reference. :-/ For instance, not counting the initial instruction opcode fetch (which is identical for all instructions), 2-byte-long 4-cycle zp,Y instructions ...


2

In some memory constrained situations (like a 4K demo or something like that), it could be useful to stop the CPU. A jam instruction is one obvious way to accomplish that in as few bytes as possible. Only the CPU will stop, so if you left some image or whatever on the screen, that's going to stay there. But another use I can think of is copy protection. ...


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